CD4536BMS Datasheet, PDF (12/13 Pages) Intersil Corporation – CMOS Programmable Timer

CD4536BMS
Applications (Continued)
VDD
A
C ^RS
B
OUT 1
C
Rtc
D
SET
START
RESET
OUT 2
8-BYPASS
C INH
MONO IN
OSC INH
IN 1
DECODE
OUT
t
f≅
1
2.3
Rtc C
RS ≥ 2Rtc
VSS
f IN Hz,
R IN Ω,
C IN F
FIGURE 22. TIME INTERVAL CONFIGURATION USING ON-
CHIP RC OSCILLATOR AND RESET INPUT
TO INITIATE TIME INTERVAL
R
CLOCK
DCBA
0000 (÷2)
0001 (÷4)
0010 (÷8)
3µs MIN
NOTE:
SHADED PULSE REPRESENTS DECODE OUTPUT
IN MONOSTABLE MODE. IF AN OUTPUT PULSE
IS REQUIRED 1 FULL COUNTDOWN AFTER
REMOVAL OF RESET PULSE, SEE FIGURE 19
FI^FG^OU^RR^UE^SE23^O.^FT^CIM^D4IN⁰⁹G^8BD^MIA^SGRAM
DECODE OUT SELECTION TABLE
NUMBER OF STAGES IN DIVIDER CHAIN
DCBA
8-BYPASS = 0
8-BYPASS = 1
0000
9
1
0001
10
2
0010
11
3
0011
12
4
0100
13
5
0101
14
6
0110
15
7
0111
16
8
1000
17
9
1001
18
10
1010
19
11
1011
20
12
1100
21
13
1101
22
14
1110
23
15
1111
24
16
0 = Low Level
1 = High Level
Functional Block Diagram
1
SET
2
RESET
OSC ¹⁴ OSC INHIBIT
INHIBIT
LOGIC
3
IN
4
OUT 1
5
OUT 2
CLOCK ⁷
INHIBIT
CLOCK INHIBIT
LOGIC
VSS = 8
VDD = 16
8-BYPASS ₆
STAGES
1-8
FIGURE 24.
8-BYPASS
LOGIC
STAGES 9-24
Q9 - - - Q24
9
A
BINARY
SELECT
10
B
11
C
12
D
15
MONO IN
DECODER
13 DECODE
OUT
7-1247