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CD4536BMS Datasheet, PDF (4/13 Pages) Intersil Corporation – CMOS Programmable Timer
Specifications CD4536BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES TEMPERATURE MIN
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V
1, 2
+125oC
-
-55oC
-
Input Voltage Low
VIL VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC, -55oC
-
Input Voltage High
VIH VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC, -55oC +7
Propagation Delay
TPHL1 VDD = 10V
Clock to Q1 8-Bypass High TPLH1 VDD = 15V
1, 2, 3
+25oC
-
1, 2, 3
+25oC
-
Propagation Delay
TPHL2 VDD = 10V
Clock to Q1 8-Bypass Low TPLH2 VDD = 15V
1, 2, 3
+25oC
-
1, 2, 3
+25oC
-
Propagation Delay
Clock to Q16
TPHL3 VDD = 10V
TPLH3 VDD = 15V
1, 2, 3
+25oC
-
1, 2, 3
+25oC
-
Propagation Delay
Qn to Qn+1
TPHL
TPLH
VDD = 5V
VDD = 10V
1, 2, 3
+25oC
-
1, 2, 3
+25oC
-
VDD = 15V
1, 2, 3
+25oC
-
Propagation Delay
Set to Qn
TPLH
VDD = 5V
VDD = 10V
1, 2, 3
+25oC
-
1, 2, 3
+25oC
-
VDD = 15V
1, 2, 3
+25oC
-
Propagation Delay
Reset to Qn
TPHL4 VDD = 10V
VDD = 15V
1, 2, 3
+25oC
-
1, 2, 3
+25oC
-
Transition Time
TTHL
TTLH
VDD = 10V
VDD = 15V
1, 2, 3
+25oC
-
1, 2, 3
+25oC
-
Maximum Clock Input
Frequency. Unlimited In-
put Rise or Fall Time
FCL VDD = 10V
VDD = 15V
1, 2, 3
+25oC
1.5
1, 2, 3
+25oC
2.5
Minimum Clock Pulse
Width
TW VDD = 5V
VDD = 10V
1, 2, 3
+25oC
-
1, 2, 3
+25oC
-
VDD = 15V
1, 2, 3
+25oC
-
Minimum Set Pulse Width TW VDD = 5V
1, 2, 3
+25oC
-
VDD = 10V
1, 2, 3
+25oC
-
VDD = 15V
1, 2, 3
+25oC
-
Minimum Reset Pulse
Width
TW VDD = 5V
VDD = 10V
1, 2, 3
+25oC
-
1, 2, 3
+25oC
-
VDD = 15V
1, 2, 3
+25oC
-
Minimum Set Recovery
Time
TREM VDD = 5V
VDD = 10V
1, 2, 3
+25oC
-
1, 2, 3
+25oC
-
VDD = 15V
1, 2, 3
+25oC
-
Minimum Reset Recov-
ery Time
TREM VDD = 5V
VDD = 10V
1, 2, 3
+25oC
-
1, 2, 3
+25oC
-
VDD = 15V
1, 2, 3
+25oC
-
Input Capacitance
CIN Any Input
1, 2
+25oC
-
MAX
-2.4
-4.2
3
-
1000
700
1600
1200
3000
2000
300
150
100
600
250
160
2000
1500
100
80
-
-
UNITS
mA
mA
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
400
ns
150
ns
100
ns
400
ns
200
ns
120
ns
6
µs
2
µs
1.5
µs
5
µs
2
µs
1.6
µs
7
µs
3
µs
2
µs
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
7-1239