CD4527BMS Datasheet, PDF (7/11 Pages) Intersil Corporation – CMOS BCD Rate Multiplier

Logic Diagram
14*
A
15*
B
2*
C
3*
D
11*
INHIBIT IN
9*
CLOCK
4*
SET TO
“9”
13*
CLEAR
CD4527BMS
T
Q
C ^AQ
R
T
Q
C ^BQ
R
T ^SQ
C ^CQ
R
T ^SQ
D
C
Q
R
VDD
VSS = 8
VDD = 16
VSS
* ^{ALL INPUTS ARE PROTECTED}
BY CMOS PROTECTION
NETWORK
*
*
STROBE CASCADE
10
12
R1
R2
OUT
6
OUT
5
R3
R4
“9”
1
INHIBIT
OUT
7
FIGURE 1.
7-1222