CD4527BMS Datasheet, PDF (10/11 Pages) Intersil Corporation – CMOS BCD Rate Multiplier

Applications
MOST SIGNIFICANT
DIGIT
DRM 1
1A
0B
OUT
0C
OUT
1D
INH.
CLOCK _OUT
CASC.
INH. IN
ST
CLEAR
“9”
S
CD4527BMS
LEAST SIGNIFICANT
DIGIT
DRM 2
0A
0B
OUT
1C
OUT
0D
INH.
CLOCK _OUT
CASC.
INH. IN
ST
CLEAR
“9”
S
CLOCK
01234567 8901234567 890
OUT
DRM 2
TIMING DIAGRAM SHOWING ONE OF FOUR OUTPUT PULSES
CONTRIBUTED BY DRM 2 TO OUTPUT FOR EVERY 100 CLOCK
PULSES IN FOR PRESET NO. 94
CLOCK
FIGURE 9. TWO CD4527BMS’s CASCADED IN THE “ADD” MODE WITH A PRESET NUMBER
( ) ^{OF 94}
9
4
94
+
=
10
100
100
DRM 1
1A
0B
OUT
0C
OUT
1D
INH.
CLOCK _OUT
CASC.
INH. IN
ST
“9”
CLEAR S
DRM 2
0A
0B
OUT
1C
OUT
0D
INH.
CLOCK _OUT
CASC.
INH. IN
ST
“9”
CLEAR S
CLOCK
FIGURE 10. TWO CD4527BMS’s CASCADED IN THE “MULTIPLY” MODE WITH A PRESET NUMBER
( ) ^{OF 36}
9
4
36
x
=
10
100
100
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
1225