X9460 Datasheet, PDF (6/16 Pages) Intersil Corporation – Dual Audio Control Digitally Controlled Potentiometer

X9460
Command Set and Register Description
Device Addressing
Following a start condition the master must output the Slave
Byte Address of the slave it is accessing. The most
significant four bits of the slave address are the device type
identifier (refer to Figure 2). For the X9460 this is fixed as
0101.
DEVICE TYPE
IDENTIFIER
0
1
0
10
A1 A0 R/W
DEVICE ADDRESS
FIGURE 2. SLAVE BYTE ADDRESS
The next three bits of the Slave Byte Address are the device
address. The device address is defined by the A₁ - A₀ inputs.
The X9460 compares the serial data stream with the Slave
Byte Address; a successful compare is required for the
X9460 to respond with an acknowledge. The A₁ - A₀ inputs
can be actively driven by CMOS input signals or tied to V_CC
or V_SS. The R/W bit sets the device for read or write
operations. Note that the X9460 supports reads and writes to
a single device on the 2-wire bus. If more than one X9460 is
used on the same 2-wire bus, those devices must have
unique device addresses and only writes are supported. You
may not read from multiple devices or contention will result
and the data is not valid.
Command Set
After a Slave Byte Address match, the next byte sent
contains the Command and register pointer information. The
four most significant bits are the Command. The next bit is a
“X” (don’t care) set to zero.
this bit not used, set to 0
Several instructions require a three-byte sequence to
complete. These instructions transfer data between the host
and the X9460. These instructions are: Read Wiper Counter
Register, Write Wiper Counter Register. The sequence of
operations is shown in Figure 4 and 5. The four-byte
command is used for write command for both right and left
pots (Figure 6).
Special Commands
Increment/Decrement Instruction. The Increment/Decrement
command is different from the other commands. Once the
command is issued and the X9460 has responded with an
acknowledge, the master can clock the selected wiper up
and/or down. For each SCL clock pulse (t_HIGH) while SDA is
HIGH, the selected wiper will move one resistor segment
towards the R_H terminal. Similarly, for each SCL clock pulse
while SDA is LOW, the selected wiper will move one resistor
segment towards the R_L terminal. A detailed illustration of
the sequence and timing for this operation are shown in
Figures 7 and 8 respectively.
Wiper Counter Register
The X9460 contains two Wiper Counter Registers. The
Wiper Counter Register output is decoded to select one of
thirty-two switches along its resistor array. The Write Wiper
Counter Register command directly sets the WCR to a
value. The Increment/Decrement instruction steps the
register value up or down one to multiple times.
The WCR is a volatile register (Table 3) and is reset to the
mute position (tap 0, “zero”) at power-up.
TABLE 3. WIPER COUNTER REGISTERS, 5-bit - VOLATILE:
WCR4
WCR3
WCR2
WCR1
WCR0
(MSB)
(LSB)
The X9460 contains one 5-bit Wiper Counter Register for
each DCP. (Two 5-bit registers in total.)
I3
I2
I1
I0
0
Z_D RT LT
INSTRUCTIONS
WIPER COUNTER
SELECT
FIGURE 3. COMMAND BYTE FORMAT
The Z_D bit enables and disables the Zero Amplitude Wiper
Switching circuit. When Z_D=1, the wiper switches will turn on
when close-to-zero amplitude is detected across the
potentiometer pins. When Z_D=0, this circuit is disabled. The
last two bits, LT (left POT enable) and RT (right POT
enable), select which of the two potentiometers is affected
by the instruction.
6
FN8203.2
October 17, 2005