X9460 Datasheet, PDF (5/16 Pages) Intersil Corporation – Dual Audio Control Digitally Controlled Potentiometer

X9460
Serial Interface Description
Serial Interface
The X9460 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. The X9460 is a slave device in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions.
Start Condition
All commands to the X9460 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X9460 continuously monitors the SDA
and SCL lines for the start condition and will not respond to
any command until this condition is met.
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
The X9460 will respond with an acknowledge: 1) after
recognition of a start condition and after an identification and
slave address byte, and 2) again after each successful
receipt of the instruction or databyte. See Figure 1.
Invalid Commands
For any invalid commands or unrecognizable addresses, the
X9460 will NOT acknowledge and return the X9460 to the
idle state.
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
ST AR T
ACKNOWLEDGE
FIGURE 1. ACKNOWLEDGE RESPONSE FROM RECEIVER
5
FN8203.2
October 17, 2005