X9118 Datasheet, PDF (6/20 Pages) Intersil Corporation – Dual Suply/Low Power/1024-Tap/2-Wire Bus

X9118
FLOW 1. ACK Polling Sequence
Nonvolatile Write
Command Completed
EnterACK Polling
Issue
START
Issue Slave
Address
Issue STOP
ACK
No
Returned?
Yes
Further
No
Operation?
Yes
Issue
Instruction
Issue STOP
Proceed
Proceed
Table 1. Identification Byte Format
Device Type
Identifies
ID3
ID2
ID1
ID0
0
1
0
1
(MSB)
INSTRUCTION AND REGISTER DESCRIPTION
DEVICE ADDRESSING: IDENTIFICATION BYTE (ID AND
A)
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier. The ID[3:0] bits is the device id for the
X9118; this is fixed as 0101[B] (refer to Table 1).
The A[1:0] bits in the ID byte are the internal slave
address. The physical device address is defined by the
state of the A1-A0 input pins. The slave address is
externally specified by the user. The X9118 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for
the X9118 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A1-A0 inputs can
Instruction and Register Description
be actively driven by CMOS input signals or tied to
V_CC or V_SS. The R/W bit is the LSB and is used to set
the device for read or write operations.
INSTRUCTION BYTE AND REGISTER SELECTION
The next byte sent to the X9118 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (I[2:0]). The RB and RA bits point to one of the
four registers. The format is shown below in Table 2.
Table 3 provides a complete summary of the
instruction set opcodes.
Set to 0
for Proper
Operation
0
Internal Slave
Address
Read or
Write Bit
0
A0
R/W
(LSB)
Table 2. Instruction Byte Format
Instruction
Opcode
I2
I1
I0
(MSB)
Set to 0
for Proper
Operation
0
Register
Selection
RB
RA
Set to 0 for
Proper Operation
0
0
(LSB)
6
FN8161.1
March 25, 2005