X1286_06 Datasheet, PDF (6/25 Pages) Intersil Corporation – Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM

X1286
AC Specifications (T_A = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.)
Symbol
Parameter
Min.
f_SCL
t_IN
t_AA
t_BUF
t_LOW
t_HIGH
t_SU:STA
t_HD:STA
t_SU:DAT
t_HD:DAT
t_SU:STO
t_DH
t_R
t_F
Cb
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus must be free before a new transmission can start
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive load for each bus line
50⁽¹⁾
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb⁽¹⁾⁽²⁾
20 +.1Cb⁽¹⁾⁽²⁾
Notes: (1) This parameter is not 100% tested.
(2) Cb = total capacitance of one bus line in pF.
Max.
400
0.9
300
300
400
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
pF
TIMING DIAGRAMS
Bus Timing
t_F
t_HIGH
t_LOW
t_R
SCL
t_SU:STA
SDA IN
SDA OUT
t_HD:STA
t_SU:DAT
t_HD:DAT
t_AA t_DH
t_SU:STO
t_BUF
6
FN8101.1
April 14, 2006