X1286_06 Datasheet, PDF (17/25 Pages) Intersil Corporation – Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM

Figure 8. Byte Write Sequence
Signals from
the Master
SDA Bus
Signals From
The Slave
X1286
S
t
a
r
Slave
t ^Address
Word
Address 1
Word
Address 0
S
t
o
Data
p
1
1110 0
A
A
A
A
C
C
C
C
K
K
K
K
Figure 9. Writing 30 bytes to a 128-byte memory page starting at address 105.
7 Bytes
23 Bytes
Address
=6
Address Pointer
Ends Here
Addr = 7
Address
105
Address
127
Figure 10. Page Write Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
Slave
t
Address
Word
Address 1
Word
Address 0
1
11 10 0
A
A
C
C
K
K
1 ≤ n ≤ 128 for EEPROM array
1 ≤ n ≤ 8 for CCR
Data
(1)
S
Data
t
(n)
o
p
A
A
C
C
K
K
17
FN8101.1
April 14, 2006