ISL6884 Datasheet, PDF (6/13 Pages) Intersil Corporation – CCFL Brightness Controller

ISL6884
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
DPWM
DPWM PLL Free Run Frequency
f_freerun
-
160
DPWM PLL Lock Frequency
f_lock
120
160
Lock Time
T_lock
-
150
DPWM Duty Cycle
DPWM_DCmin BRT_M = 00hex (Note 3)
3
4
DPWM Duty Cycle
DPWM_DCmid BRT_M = 7Fhex (Note 3)
49
50
DPWM Duty Cycle
DPWM_DCmax BRT_M = FFhex (Note 3)
98
-
DPWM Output High
V_OH
I_OH = 2mA
0.7*VDD
-
DPWM Output Low
V_OL
I_OL = 2mA
-
-
DPWM Rise Time
T_{rise_DPWM} Cload = 200pF
-
-
DPWM Fall Time
T_{fall_DPWM} Cload = 200pF
-
-
NOTE:
2. Master enable (0X2B) = 01, channel enable (0X2C) = FF, all other registers in default mode
MAX UNITS
-
Hz
200
Hz
-
ms
5
%
51
%
100
%
-
V
0.3*VDD
V
500
ns
500
ns
Pin Description
VDD - Power input for digital systems. All functions are
disabled unless this pin exceeds 3V (see Power On Reset
specs). A 0.01µF decoupling cap should be placed between
VDD and GND with the shortest possible traces.
GND - Ground for digital systems.
REGCAP - An external 1µF capacitor to decouple the
internal 2.5V regulator.
EN - Logic level input signal. Voltage at this pin above a
threshold ENables circuit operation.
DPWM SYNC - A logic level input signal. The dimming PWM
frequency oscillator will synchronize to this signal (if
present). If no signal is present at this pin, the internal
DPWM oscillator will free run at approximately 160Hz.
PLL1 - Analog input. An RC network on these pins sets the
loop response of the DPWM Phase Locked Loop. A voltage
source or resister divider at this pin will set the DPWM
frequency. See the graph below for approximate frequency
vs voltage at PLL1.
220
200
180
160
140
120
100
80
60
0.5
F_DPWM=V_PLL1*160+8
measured
0.7
0.9
1.1
1.3
Voltage at PLL1 (V)
GNDPLL - A separate ground terminal for the PLL. Filter
and bias components on PLL1 should be connected to this
ground with the shortest possible traces. This pin is also
connected to the system ground with a trace that is not
critical.
DPWM 1:8 - Logic level outputs that control the analog and
PWM dimming of each of 8 ISL6882s. The duty cycle of the
DPWM signals range from 4% (minimum brightness) to
100% (maximum brightness). A low pass filter in the inverter
Controller converts the DPWM duty cycle to a DC voltage
that performs 3:1 analog dimming. The combined dimming
range is 100:1. The dimming value is set by I²C registers.
LAMP_ON - A logic level input signal. A high level on the pin
indicates that all lamps are ON and operating normally. A low
level at this pin indicates that at least one of the lamps is
either not ignited or out of the circuit. When this pin is low,
the fault timer runs. When this pin is high, the fault timer is
reset. Because this is a high impedance line that may be
routed near sources of EMI, it is recommended that a 10K
resister is placed in series between the LAMP_ON pin and
all other circuits.
SDA, SCL - Logic level input/output signals. SDA is the I²C
data line and SCL is the I²C clock line. The ISL6884
receives data via I²C to enable or disable the inverters, set
dimming for each channel, and set the number of channels.
System status can be read via I²C.
TESTEN and OSCTEST - These pins are used for internal
tests. They should be left unconnected in normal operation.
6
FN9265.0
March 9, 2006