ISL6884 Datasheet, PDF (10/13 Pages) Intersil Corporation – CCFL Brightness Controller

ISL6884
TABLE 1. REGISTER DESCRIPTION TABLE (READ/WRITE REGISTERS) (Continued)
WORD NAME
DESCRIPTION
BYTE
ADDRESS MSB LABEL BIT 6 LABEL BIT 5 LABEL BIT 4 LABEL BIT 3 LABEL BIT 2 LABEL BIT 1 LABEL LSB LABEL
POR
POR VALUE POR VALUE POR VALUE POR VALUE POR VALUE POR VALUE POR VALUE POR VALUE
0x37
b7
b6
b5
b4
b3
b2
b1
b0
POR
0
0
0
0
1
0
0
1
pwm_
sync_sel
PWM Sync Mode Select.
PWM_SYNC_SEL = xxxxxx00: INTERNAL ONLY. DPWM frequency set by an internal oscillator. External DPWM_SYNC is
ignored.
PWM_SYNC_SEL = xxxxxx01: AUTOMATIC SYNC SELECT. DPWM frequency set by an external DPWM_SYNC signal if it is
present or by the internal oscillator if no external signal is present.
PWM_SYNC_SEL = xxxxxx10: EXTERNAL ONLY. DPWM frequency set by an external signal at DPWM_SYNC. No signal at
DPWM_SYNC results in no DPWM output switching.
0x38
pwm_sync
_sel2
pwm_sync
_sel1
POR
0
0
0
0
0
0
0
1
pll_bypass
pmp1
pmp0
Bypass PLL bit = 1 forces DPWM frequency to an internal oscillator.
Charge Pump Bit1. See Plan 9 CDR Document for description.
Charge Pump Bit0. See Plan 9 CDR Document for description.
Caution! Changing this register from its default value may result in unpredictable behavior
0x39
pll_bypass
pmp1
pmp0
POR
0
0
0
0
0
0
0
0
Mux Selection for test mode mux. If the part is in test mode, the decode of this value changes the following pins:mx_sel = 0: dpwm6, dpwm7,
dpwm8 in functional mode.
mx_sel = 1: dpwm6 = vco_out, dpwm7 = div512_out, dpwm8 = div64_clk.
mx_sel = 2: dpwm6 in functional mode, dpwm7 = clk_d4, dpwm8 = dpwm_clk.
Caution! Changing this register from its default value may result in unpredictable behavior
0x3A
mx_sel
b3
b2
b1
b0
POR
0
0
0
0
0
0
0
0
10
FN9265.0
March 9, 2006