ISL6884 Datasheet, PDF (11/13 Pages) Intersil Corporation – CCFL Brightness Controller

ISL6884
I²C Bus General Description
Introduction
(Refer to Philips I²C Specification, Rev. 2.1)
The I²C bus is a 2 wire communication bus for integrated
circuits. I²C, I2C or IIC are commonly used instead of the
formal name Inter-Integrated-Circuit bus. The 2 wires are the
SCL (Serial CLock) and SDA (Serial DAta). All ICs on the
bus are connected to the SCL and SDA lines. SCL and SDA
pins on each device are bidirectional and can act as either
inputs or open drain outputs. Which device is transmitting
and receiving is determined by the bus protocol which will be
described below.
VDD
CPU
I2C Master
input
SCL
control output
input
SDA
control output
I2C Slave
input
SCL
output control
input
SDA
output control
state
machine,
registers,
memory,
etc.
I2C Slave
input
SCL
output control
input
SDA
output control
state
machine,
registers,
memory,
etc.
to other
slave devices
A typical I²C bus system is made of a ‘master’ that initiates
communication (usually a microprocessor) and one or more
‘slaves’ that respond to commands from the master. Each
slave has a device address. In a typical communication
sequence, the master will initiate communication with a ‘start
condition’ followed by the address of one of the slave
devices. The slave device must acknowledge that it
recognizes its address. After receiving the acknowledge, the
master will transmit one or more bytes of commands and
data. If the slave device is an EEPROM the command is the
address within the EEPROM that is to be read or written. If
data is to be written to the EEPROM the master transmits it
after the command.
START and STOP Conditions
As shown in Figure 1, START condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent
before each START condition.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is
LOW. Refer to Figure 2.
SDA
SCL
DATA LINE CHANGE
STABLE OF DATA
DATA VALID ALLOWED
FIGURE 2. DATA VALIDITY
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 3).
The peripheral that acknowledges has to pull down (LOW)
the SDA line during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
SCL
SDA
START
1
2
8
9
MSB
ACKNOWLEDGE
FROM SLAVE
FIGURE 3. ACKNOWLEDGE ON THE I²C BUS
SDA
SCL
S
P
START
CONDITION
STOP
CONDITION
FIGURE 1. START AND STOP WAVEFORMS
11
FN9265.0
March 9, 2006