ISL6548A_06 Datasheet, PDF (6/16 Pages) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems

ISL6548A
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
PWM CONTROLLER GATE DRIVERS
UGATE and LGATE Source
UGATE and LGATE Sink
VTT REGULATOR
I_GATE
I_GATE
- -0.8 -
A
-
0.8
-
A
Upper Divider Impedance
Lower Divider Impedance
Maximum V_TT Load Current
R_U
-
2.5
-
kΩ
R_L
-
2.5
-
kΩ
I_{VTT_MAX} Periodic load applied with 30% duty cycle and
-3
-
3
A
10ms period using ISL6548A_6506EVAL1
evaluation board (see Application Note AN1124)
LINEAR REGULATORS
DC Gain
Guaranteed By Design
-
80
-
dB
Gain Bandwidth Product
GBWP
15
-
-
MHz
Slew Rate
SR
-
6
-
V/µs
DRIVEn High Output Voltage
DRIVEn Unloaded
9.75 10.0 -
V
DRIVEn Low Output Voltage
- 0.16 0.50
V
DRIVEn High Output Source Current
DRIVEn Low Output Sink Current
VIDPGD
V_FB = 770mV, V_DRIVEn = 0V
V_FB = 830mV, V_DRIVEn = 10V
-
1.7
-
mA
- 1.20 -
mA
V_{TT_GMCH/CPU} Rising Threshold
S0
V_{TT_GMCH/CPU} Falling Threshold
S0
PROTECTION
.725 .740 -
V
- 0.700 0.715 V
OCSET Current Source
V_{TT_DDR} Current Limit
V_DDQ OV Level
V_DDQ UV Level
V_{TT_DDR} OV Level
V_{TT_DDR} UV Level
V_GMCH UV Level
V_{TT_GMCH/CPU} UV Level
Thermal Shutdown Limit
I_OCSET
By Design
V_FB/V_REF S0/S3
V_FB/V_REF S0/S3
V_TT/V_{VREF_IN} S0
V_TT/V_{VREF_IN} S0
V_FB4/V_REF S0
V_FB2/V_REF S0
T_SD
By Design
18 20 22
µA
-3.3 -
3.3
A
- 115 -
%
-
85
-
%
- 115 -
%
-
85
-
%
-
85
-
%
-
85
-
%
- 140 -
°C
Functional Pin Description
5VSBY (Pin 1)
5VSBY is the bias supply of the ISL6548A. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6548A enters a reduced
power mode and draws less than 1mA (I_{CC_S5}) from the
5VSBY supply. The supply to 5VSBY should be locally
bypassed using a 0.1µF capacitor.
P12V (Pin 3)
The V_TT regulation circuit and the Linear Drivers are
powered by P12V. P12V is not required during S3/S4/S5
operation. P12V is typically connected to the +12V rail of an
ATX power supply.
GND (Pins 4, 27, 29)
The GND terminals of the ISL6548A provide the return path
for the V_TT LDO, and switching MOSFET gate drivers. High
ground currents are conducted directly through the exposed
paddle of the QFN package which must be electrically
connected to the ground plane through a path as low in
inductance as possible.
6
FN9189.2
January 3, 2006