ISL6548A_06 Datasheet, PDF (12/16 Pages) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems

ISL6548A
12V_ATX
P12V
GNDP
5VSBY
ISL6548A
UGATE
PHASE
C_BP
5VDUAL
5VSBY
C_BP
C_IN
Q₁ ^L1
V_DDQ
LGATE
COMP
FB
VDDQ(2)
VTT(2)
Q₂
C_OUT1
C₂
R₂
C₁
R₁
R₄ ^{C3 R}3
V_DDQ
V_TT
C_OUT2
3.3VATX
PWM4
C_IN
Q₁
Q₂
L₂
V_GMCH
COMP4
FB4
C₆
R₆
C₅
R₅
R₈ ^{C7 R}7
C_OUT3
DRIVE2_U
FB2
R₉
R₁₀
Q₃
V_{TT_GMCH/CPU}
Q₃
C_OUT4
DRIVE2_L
DRIVE3
FB3
GND PAD
R₁₁
R₁₂
3.3VATX
Q₃
V_ICH7
C_OUT5
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 2. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
the heat to move away from the IC and also ties the pad to
the ground plane through a low impedance path.
The switching components should be placed close to the
ISL6548A first. Minimize the length of the connections
between the input capacitors, C_IN, and the power switches
by placing them nearby. Position both the ceramic and bulk
input capacitors as close to the upper MOSFET drain as
possible. Position the output inductor and output capacitors
between the upper and lower MOSFETs and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB
pin with vias tied straight to the ground plane as required.
Feedback Compensation - PWM Buck Converters
Figure 3 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V_OUT) is regulated to the Reference voltage level. The error
amplifier output (V_E/A) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of V_IN at the PHASE node. The
PWM wave is smoothed by the output filter (L_O and C_O).
∆ V_OSC
OSC
PWM
COMPARATOR
-
+
DRIVER
DRIVER
V_IN
L_O
PHASE _CO
V_DDQ
Z_FB
V_E/A
-
+
Z_IN
ERROR ^REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C₁
C₂
R₂
Z_FB
V_DDQ
Z_IN
C₃ R₃
COMP
R₁
-
FB
+
R₄
ISL6548A
REFERENCE
V_DDQ
=
0.8
×



1
+
RR-----_{14-}
FIGURE 3. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
12
FN9189.2
January 3, 2006