ISL6548A_06 Datasheet, PDF (13/16 Pages) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems

ISL6548A
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A. This function is dominated by a DC
Gain and the output filter (L_O and C_O), with a double pole
break frequency at F_LC and a zero at F_ESR. The DC Gain of
the modulator is simply the input voltage (V_IN) divided by the
peak-to-peak oscillator voltage ∆V_OSC.
Modulator Break Frequency Equations
FLC=
---------------------¹---------------------
2π x LO x CO
FESR=
---------------------¹----------------------
2π x ESR x CO
The compensation network consists of the error amplifier
(internal to the ISL6548A) and the impedance networks Z_IN
and Z_FB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f_0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f_0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R₁, R₂,
R₃, C₁, C₂, and C₃) in Figure 3. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R₂/R₁) for desired converter bandwidth.
2. Place 1^ST Zero Below Filter’s Double Pole (~75% F_LC).
3. Place 2^ND Zero at Filter’s Double Pole.
4. Place 1^ST Pole at the ESR Zero.
5. Place 2^ND Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
F_Z1
=
-----------------1------------------
2π x R₂ x C₁
F_Z2 = _2----π------x-----₍--R-----₁----+-1----R-----₃---₎----x-----C-----₃-
F_P1
=
---------------------------1-----------------------------
2π
x
R₂
x



C-C----_{11-----+x-----CC----2-2-}
F_P2 = -2---_π------x-----R--1--₃------x-----C----₃-
Figure 4 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 4. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F_P2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 4 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
100
F_Z1 F_Z2 F_P1 F_P2
80
OPEN LOOP
60
ERROR AMP GAIN
40
20LOG
20 ^(R2^/R1⁾
20LOG
0
(V_IN/∆V_OSC)
MODULATOR
-20
GAIN
-40
F_LC
F_ESR
-60
10
100
1K
10K 100K
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M 10M
FREQUENCY (Hz)
FIGURE 4. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Output Voltage Selection
The output voltage of the all the external voltage regulators
converter can be programmed to any level between their
individual input voltage and the internal reference, 0.8V. An
external resistor divider is used to scale the output voltage
relative to the reference voltage and feed it back to the
inverting input of the error amplifier, refer to the Typical
Application on page 4.
The output voltage programming resistor will depend on the
value chosen for the feedback resistor and the desired
output voltage of the particular regulator.
R4 = _V-----RD----_D^1----_Q-^×-----_–^{0---.-0-8---.-V8----V--}
R8 = -V----_G--R--_M---5--_C---^×-_H----0--_–-.--8-0--V-.--8----V--
R10 = -V----_Tx---_Tx---_{x_}---_xG--R-_x-_M--_x-9-_C-_x---_x^×_H---_x-_/-0_C-_x--.-_xP-8--_x-_U-V--_–-----0---.--8----V--
R12 = -V--R--_D--1--_A--1--_C---^×--_–--0---0-.-8-.--8-V--V---
If the output voltage desired is 0.8V, simply route the output
voltage back to the respective FB pin through the feedback
resistor and do not populate the output voltage programming
resistor.
The output voltage for the internal V_{TT_DDR} linear regulator
is set internal to the ISL6548A to track the V_DDQ voltage by
50%. There is no need for external programming resistors.
13
FN9189.2
January 3, 2006