ISL6401_14 Datasheet, PDF (6/11 Pages) Intersil Corporation – Synchronizing Current Mode PWM for Subscriber Line Interface Circuits (SLICs)

ISL6401
higher, depending on the output current. Total V_CC current is
the sum of the quiescent V_CC current and the average
output current. Knowing the operating frequency and the
MOSFET gate charge (Qg), average output current can be
calculated from:
I_OUT = Qg × F
To prevent noise problems, bypass V_CC to GND with a
ceramic capacitor as close to the V_CC pin as possible. An
electrolytic capacitor may also be used in addition to the
ceramic capacitor.
Functional Description
Features
The ISL6401 current mode, synchronizable PWM, makes an
ideal choice for low-cost, low-power, multi-output flyback
topology applications with low input-output ripple current
requirements. When configured in a multi-winding flyback
topology, the IC is capable of generating the negative Talk
and Ring voltages required for Ringing Subscriber Line
Interface (RSLIC) power supplies. This approach provides
dual outputs from a single power switch and control IC. Low
current sense voltage and shutdown mode leads to high
efficiency operation. Other features include peak current
mode control, internal soft-start, adjustable current limit,
adjustable frequency and external frequency
synchronization.
Oscillator
The ISL6401 has an internal sawtooth oscillator with a
programmable frequency range of 100kHz to 1MHz, which
can be programmed with a capacitor on the CT pin. (Please
refer to Figure 4 for the capacitance required for a given
frequency.) With a maximum 50% duty cycle operation, the
output switching frequency is half the oscillator frequency.
Implementing Synchronization
The oscillator can be synchronized by an external clock
inserted at the SYNC pin. Program the free running
frequency of the oscillator to be 10% slower than the desired
synchronous frequency. The external clock signal should
have a minimum pulse width of 20ns.
Soft-Start Operation
The ISL6401 features an internal digital soft-start with no
external capacitor required. Soft-start is used to reduce
transformer and output capacitor stress and to reduce the
surge on the input circuits, when the converter action starts.
The considerable capacitance on the output lines should be
charged slowly, so as not to reflect an excessive transient. A
very wide initial pulse could result in saturation of the core
and voltage overshoot on the output, if the inductor current is
allowed to rise to a high value during start-up.
Upon start-up, the peak primary current increments from
1/5th of the value set by R_CS to the full current limit value in
steps, over 2048 cycles of Fosc or Fsync. Soft-start clamps
the error amplifier output (COMP pin) and the reference
input (non-inverting terminal of the error amplifier) to the
internally generated soft-start voltage. The oscillator
sawtooth waveform is compared to the ramping error
amplifier voltage. This generates GATE pulses of increasing
width that charge the output capacitor(s). With sufficient
output voltage, the clamp on the reference input controls the
output voltage. When the internally generated soft-start
voltage exceeds the FB pin voltage, the output voltage is in
regulation. This method provides a rapid, controlled output
voltage rise. Soft-start is implemented during start-up, after
an overcurrent has cleared, or when exiting shutdown or
undervoltage lock-out (UVLO).
Gate Drive
The ISL6401 is capable of sourcing 1A of peak-drive current.
Separate collector supply (PV_CC) and power ground (PGnd)
pins help isolate the IC’s analog circuitry from the high power
gate drive noise. To limit the peak current through the IC, an
external resistor is placed between the totem-pole output of
the IC and the gate of the MOSFET. The minimum value of
this resistor is determined by:
Rgate = (Vdd(min) - Vsat) / Igate(peak)
This small series resistor also damps any oscillations
caused by the resonant tank of the parasitic inductances in
the traces of the board and the FET’s input capacitance. A
pull-down resistor is sometimes added to the gate drive to
insure the MOSFET gate does not get charged to its turn-on
threshold during device start-up. Adding a fast-switching
diode and smaller value resistor in parallel with the gate
resistor helps to control the current the IC needs to sink
during turn-off and protects the output stage of the device.
These components also help to reduce turn-off losses, which
tend to dominate the switching losses in discontinuous
current-mode (DCM) converters.
Ground Plane Requirements
Careful layout is essential for correct operation of the device.
A good ground plane must be employed. A unique section of
the ground plane must be designated for high di/dt currents
associated with the output stage. Power ground (PGND) can
be separated from the analog ground (GND) and connected
at a single point. V_CC should be bypassed directly to PGND
with good high frequency capacitors. The return connection
for input power to the system and the bulk input capacitor
should be connected to the PGND ground plane.
Application Information
Subscriber Line Interface Circuit Requirements
As worldwide demand for inexpensive Voice over Internet
Protocol telephony grows, so will the need for ICs that
enable compatibility between new telephony systems and
older telephones based on analog standards. Old style
telephones require signal and power inputs that are not
generally available on purely digital systems. Analog ring
6
FN9007.7
April 13, 2005