ISL6401_14 Datasheet, PDF (5/11 Pages) Intersil Corporation – Synchronizing Current Mode PWM for Subscriber Line Interface Circuits (SLICs)

Typical Performance Curves (Continued)
ISL6401
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-40
-20
25
60
85
TEMPERATURE (°C)
FIGURE 3. SUPPLY CURRENT vs TEMPERATURE
Pin Descriptions
SD - This pin is logic level compatible and can be pulled
high, tied to V_IN or left open for normal operation. Logic low
on the SD activates shutdown, reducing the part’s supply
current to approximately 55µA.
SYNC - This pin is the input pin for external frequency
synchronization. The switching frequency of the device can
be synchronized by an external clock signal inserted at this
pin. The oscillator timing capacitor, C_T, is still required, even
if an external clock is used. Program the free-running
frequency to be a minimum of 10% slower than the SYNC
input frequency.
CT - This is the oscillator timing pin. The free-running
frequency can be set by connecting a timing capacitor to this
pin. The oscillator produces a sawtooth waveform with a
programmable frequency range of 100kHz to 1.2MHz.
Figure 4 may be used as a guideline in selecting the
capacitor value required for a given frequency.
COMP - COMP is the output of the error amplifier and input
of the current comparator.
The ISL6401 features built-in full cycle soft-start. Soft-start is
implemented as a clamp on the maximum COMP voltage.
FB - Feedback pin that is used for positive output voltage
sensing. It is the inverting input of the error amplifier. The
non-inverting input of the error amplifier is internally tied to a
reference voltage.
NFB-IN - Negative feedback pin that is used for negative
output voltage sensing. It is connected to the inverting input
of the negative feedback amplifier through a 100K source
resistor.
NFB OUT - This pin is the output of the negative feedback
inverter. This pin should be connected the FB pin with a 10K
5
600
500
400
300
200
100
0
82
120 180 250 300 390 510 610 820 1200
CAPACITANCE (pF)
FIGURE 4. CAPACITANCE vs FREQUENCY
series resistor for negative output voltage regulation
applications.
CS - This is the input of the current sense comparator. The
IC has two different comparators: The PWM comparator and
an overcurrent comparator.
The overcurrent comparator is only intended for fault
sensing, and exceeding the overcurrent threshold will cause
a soft-start cycle.
GND - GND is a small signal reference ground for all analog
functions on this part.
PGND - This pin provides a dedicated ground for the output
gate driver. The GND and PGND pins should be connected
externally using a short printed circuit board trace close to
the IC. This is imperative to prevent large, high frequency
switching currents flowing through the ground metallization
inside the IC. (Decouple PV_CC to PGND with a low ESR
0.1µF capacitor.)
GATE - This is the device output. It is a high current power
driver capable of driving the gate of a power MOSFET with
peak currents exceeding 1.0A. This GATE output is actively
held low when V_CC is below the UVLO threshold (3.7V typ).
The high-current power driver consists of FET output
devices, which can switch all the way to GND and all the way
to V_CC. The output stage also provides very low impedance
to overshoot and undershoot.
PV_CC - This pin is for separate collector supply to the output
gate drive. Separate PV_CC and PGnd helps decouple the
IC’s analog circuitry from the high power gate drive noise.
Connect this pin to V_CC with external short trace on printed
circuit board.
V_CC - V_CC is the power connection for the device. Although
quiescent V_CC current is very low, total supply current will be
FN9007.7
April 13, 2005