ISL54416 Datasheet, PDF (6/14 Pages) Intersil Corporation – Low Voltage, Dual SPDT, USB/CVBS/ Audio Switches with Negative Signal Capability

ISL54415, ISL54416, ISL54417
Electrical Specifications - 2.7V to 5.5V Supply Test Conditions: V_DD = +3.0V, GND = 0V, V_BUSH = 3.8V, V_BUSL = 3.2V,
V_INH = 1.4V, V_INL = 0.5V (Notes 4, 6), Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
TEMP (NOTE 5)
(NOTE 5)
(°C)
MIN
TYP MAX UNITS
POWER SUPPLY CHARACTERISTICS
Power Supply Range, V_DD
(ISL54415 and ISL54416 Only)
Full
2.5
-
3.6
V
Power Supply Range, V_DD
(ISL54417 Only)
Full
1.8
-
5.5
V
Positive Supply Current, I_DD
Audio/Video Mode
(ISL54415 and ISL54416 Only)
V_DD = 3.6V, V_BUS = Float
25
-
4.5
8
μA
Full
-
-
10
μA
Positive Supply Current, I_BUS
USB Mode
(ISL54415 and ISL54416 Only)
V_DD = 3.6V, V_BUS = 5.25V
25
-
3.5
8
μA
Full
-
-
25
μA
Positive Supply Current, I_DD
(ISL54417 Only)
V_DD = 5.5V, V_IN = 0V
25
-
Full
-
8
11
μA
-
15
μA
Positive Supply Current, I_DD
(ISL54417 Only)
V_DD = 5.5V, V_IN = 5.5V
25
-
0.06
0.5
μA
Full
-
-
1
μA
Positive Supply Current, I_DD
(ISL54417 Only)
V_DD = 5.5V, V_IN = 2.85V
25
-
5.5
8
μA
Full
-
-
10
μA
V_TERM Voltage, V_VTERM
(ISL54415 Only)
V_DD = 2.5V, V_BUS = 4.4V, R_TERM = 16.5kΩ to Ground
25
3.0V
-
3.6V
V
V_TERM Voltage, V_VTERM
(ISL54415 Only)
V_DD = 2.0V, V_BUS = 4.4V
25
0V
-
0.5V
V
DIGITAL INPUT CHARACTERISTICS
V_BUS Voltage Low, V_BUSL
(ISL54415 and ISL54416 Only)
Full
-
-
V_DD +
V
0.2
V_BUS Voltage High, V_BUSH
(ISL54415 and ISL54416 Only)
Full V_DD + 0.8 -
-
V
Input Voltage Low, V_INL
(ISL54417 Only)
V_DD = 2.7V to 3.6V
Full
-
-
0.5
V
Input Voltage High, V_INH
(ISL54417 Only)
V_DD = 2.7V to 3.6V
Full
1.4
-
-
V
Input Voltage Low, V_INL
(ISL54417 Only)
V_DD = 5.0V
Full
-
-
0.8
V
Input Voltage High, V_INH
(ISL54417 Only)
V_DD = 5.0V
Full
2.3
-
-
V
Input Current, I_INH, I_INL
(ISL54417 Only)
V_DD = 5.5V, V_IN = 0V or V_DD
Full
-
0.1
-
μA
NOTES:
4. V_IN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
8. Guaranteed by design.
9. R_ON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max R_ON
value between NC1 and NC2 or between NO1 and NO2.
6
FN6318.1
June 27, 2006