DG401_06 Datasheet, PDF (6/12 Pages) Intersil Corporation – Monolithic CMOS Analog Switches

Test Circuits and Waveforms (Continued)
SIGNAL
GENERATOR
+15V ^+5V
C V+
V_L C
V_S1
V_D1
50Ω
0V, 2.4V
IN₁
IN₂
0V, 2.4V
ANALYZER
R_L
V_D2
V_S2
NC
C
GND ^V-
-15V
FIGURE 6. CROSSTALK TEST CIRCUIT
Application Information
Dual Slope Integrators
The DG403 is well suited to configure a selectable slope
integrator. One control signal selects the timing capacitor C₁
or C₂. Another one selects e_IN or discharges the capacitor in
preparation for the next integration cycle.
+5V
+15V
V_L
V+
e_IN
S₁
D₁
S₃
D₂
e_OUT
INTEGRATE/
TTL
RESET
SCOPE
SELECT
IN₁
S₂
D₃
C₁
S₄
D₄
IN₂
C₂
DG403
GND
V-
-15V
FIGURE 8. DUAL SLOPE INTEGRATOR
+15V
C V+
+5V
V_L C
IMPEDANCE
ANALYZER
V_S
0V, 2.4V
IN_X ^{AS REQUIRED}
V_D
C
GND
V-
-15V
FIGURE 7. CAPACITANCES TEST CIRCUIT
Peak Detector
A₃ acting as a comparator provides the logic drive for
operating SW₁. The output of A₂ is fed back to A₃ and
compared to the analog input e_IN. If e_IN > e_OUT the output of
A₃ is high keeping SW₁ closed. This allows C₁ to charge up
to the analog input voltage. When e_IN goes below e_OUT, A₃
goes negative, turning SW₁ off. The system will therefore
store the most positive analog input experienced.
RESET
+- ^A1
e_IN
+
-
A₃
SW₂
SW₁
R₁
C₁
DG401
A_{2 eOUT}
+
-
FIGURE 9. POSITIVE PEAK DETECTOR
6
FN3284.11
November 20, 2006