DG401_06 Datasheet, PDF (5/12 Pages) Intersil Corporation – Monolithic CMOS Analog Switches

Test Circuits and Waveforms (Continued)
3V
LOGIC
INPUT
0V
V_S1
SWITCH
OUTPUT
(V_O1) _0V
V_S2
SWITCH
OUTPUT
(V_O2) _0V
90%
t_D
90%
t_D
V_S1 = 10V
V_S2 = 10V
IN₁
LOGIC
INPUT
5V
V_L
+15V
V+
R_L = 300Ω
C_L = 35pF
D₁
V_O1
D₂ V_{O2 RL1}
C_L1
GND
R_L2
C_L2
V-
0V
-15V
C_L includes fixture and stray capacitance.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. BREAK-BEFORE-MAKE TIME
SWITCH
OUTPUT
V_O
ΔV_O
IN_X ^ON
OFF
ON
R_G
V_G
Q = ΔV_O x C_L
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3. CHARGE INJECTION
5V
V_L
+15V
V+
D₁
GND
V-
0V
-15V
FIGURE 3B. TEST CIRCUIT
V_O
C_L
SIGNAL
GENERATOR
+15V +5V
C V+
V_L C
V_S
IN_X
0V, 2.4V
ANALYZER
V_D
R_L
C
GND
V-
-15V
FIGURE 4. OFF ISOLATION TEST CIRCUIT
SIGNAL
GENERATOR
+15V +5V
C V+
V_L C
V_S
IN_X
0V, 2.4V
ANALYZER
R_L
V_D
C
GND
V-
-15V
FIGURE 5. INSERTION LOSS TEST CIRCUIT
5
FN3284.11
November 20, 2006