CD4014BMS Datasheet, PDF (6/9 Pages) Intersil Corporation – CMOS 8-Stage Static Shift Registers

Specifications CD4014BMS, CD4021BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS (Continued)
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 2 (Note 1)
2, 3, 12
8
1, 4-7, 9-11, 13-6
Dynamic Burn-In (Note 1)
-
1, 4-9, 13 -15
16
2, 3, 12
10
11
Irradiation (Note 2)
2, 3, 12
8
1, 4-7, 9-11, 13-16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD =
10V ± 0.5V
Logic Diagram
P1
7_*
P2
6_*
P3
5_*
P4
4_*
P5
13 _*
P6
14 _*
P7
15 _*
P8
1_*
SERIAL
INPUT
* ¹¹
CLOCK
* ¹⁰
PARALLEL/SERIAL
CONTROL
*⁹
P
P
DQ
P
DQ
P
DQ
P
DQ
P
DQ
P
DQ
P
DQ
P
DQ
CL
PS
CL
PS
CL
PS
CL
PS
CL
PS
CL
PS
CL
PS
CL
PS
P
DQ
≡
CL
D
PS
PS
p
CL
C
CL
n
CL
CL
p
p
n
n
p
CL
n
CL
CL
VDD
p
n
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
CL
VSS
FIGURE 1. CD4014BM LOGIC DIAGRAM
TRUTH TABLE - CD4014BMS
CL
SERIAL INPUT
X
X
X
X
0
1
X
X = Don’t Care Case
PARALLEL/SERIAL CONTROL PI-1
PI-n
1
0
0
1
1
0
1
0
1
1
1
1
0
X
X
0
X
X
X
X
X
NC = No Change
2
Q6
CL
p
n
CL
Q1 (INTERNAL)
0
1
0
1
0
1
Q1
2
3
Q7
Q8
Q
Qn
0
0
1
1
Qn-1
Qn-1
Qn NC
7-85