CD4014BMS Datasheet, PDF (1/9 Pages) Intersil Corporation – CMOS 8-Stage Static Shift Registers

CD4014BMS,
CD4021BMS
December 1992
CMOS 8-Stage Static Shift Registers
Features
Description
• High Voltage Types (20V Rating)
CD4014BMS -Synchronous Parallel or Serial Input/Serial Output
• Medium Speed Operation 12MHz (Typ.) Clock Rate at CD4021BMS -Asynchronous Parallel Input or Synchronous
VDD-VSS = 10V
Serial Input/Serial Output
• Fully Static Operation
• 8 Master-Slave Flip-Flops Plus Output Buffering and
Control Gating
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25^oC
• Noise Margin (Full Package Temperature Range)
• 1V at VDD = 5V
• 2V at VDD = 10V
• 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
`B' Series CMOS Devices
Applications:
CD4014BMS and CD4021BMS series types are 8-stage paral-
lel- or serial-input/serial output registers having common CLOCK
and PARALLEL/SERIAL CONTROL inputs, a single SERIAL
data input, and individual parallel “JAM” inputs to each register
stage. Each register stage is a D-type, master-slave flip-flop. In
addition to an output from stage 8, “Q” outputs are also available
from stages 6 and 7. Parallel as well as serial entry is made into
the register synchronously with the positive clock line transition in
the CD4014BMS. In the CD4021BMS serial entry is synchro-
nous with the clock but parallel entry is asynchronous. In both
types, entry is controlled by the PARALLEL/SERIAL CONTROL
input. When the PARALLEL/SERIAL CONTROL input is low,
data is serially shifted into the 8-stage register synchronously
with the positive transition of the clock line. When the PARALLEL/
SERIAL CONTROL input is high, data is jammed into the 8-
stage register via the parallel input lines and synchronous with
the positive transition of the clock line. In the CD4021BMS, the
CLOCK input of the internal stage is “forced” when asynchro-
nous parallel entry is made. Register expansion using multiple
packages is permitted.
The CD4014BMS and CD4021BMS are supplied in these 16
lead outline packages:
• Parallel Input/Serial Output Data Queueing
• Parallel to Serial Data Conversion
• General Purpose Register
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1F
H6W
Pinout
PI-8 1
Q6 2
Q8 3
PI-4 4
PI-3 5
PI-2 6
PI-1 7
VSS 8
16 VDD
15 PI-7
14 PI-6
13 PI-5
12 Q7
11 SERIAL IN
10 CLOCK
9 PARALLEL/SERIAL
CONTROL
Functional Diagram
PAR. IN
VDD
12345678
7 6 5 4 13 14 15 1 16
PARALLEL/SERIAL ⁹
CONTROL
11
SERIAL IN
10
CLOCK
2
Q6
12 _Q7
3
Q8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-80
8
VSS
File Number 3294