CD4013BMS Datasheet, PDF (6/9 Pages) Intersil Corporation – CMOS Dual ‘D’-Type Flip-Flop

Specifications CD4013BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 1
(Note 1)
OPEN
1, 2, 12, 13
GROUND
3-11
VDD
14
9V ± -0.5V
50kHz
25kHz
Static Burn-In 2
(Note 1)
1, 2, 12, 13
7
3-6, 8-11, 14
Dynamic Burn-
-
4, 6-8, 10
14
1, 2, 12, 13
3, 11
5, 9
In (Note 1)
Irradiation
(Note 2)
1, 2, 12, 13
7
3-6, 8-11, 14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagram
*4(10)
RESET
CL
p
*5(9)
TG
DATA
n
CL
*6(8)
SET
CL
*3(11)
CL
14
VDD
7
VSS
MASTER SECTION
CL
p
TG
n
CL
CL
CL _{SLAVE SECTION}
p
TG
n
CL
CL
p
TG
n
CL
Q
1(13)
BUFFERED OUTPUTS
Q
2(12)
* All inputs are protected by CMOS protection network
FIGURE 1. ONE OF TWO IDENTICAL FLIP-FLOPS
TRUTH TABLE
CL* D R S Q Q
00001
10010
X 0 0 QQ
X
X1001
X
X0110
X
X1111
Logic 0 = Low
Logic 1 = High
* = Level change
X = Don’t care
N(N) = FF1/FF2 terminal assignments
No
Change
7-67