CD4013BMS Datasheet, PDF (1/9 Pages) Intersil Corporation – CMOS Dual ‘D’-Type Flip-Flop

CD4013BMS
December 1992
CMOS Dual ‘D’-Type Flip-Flop
Features
Pinout
• High-Voltage Type (20V Rating)
• Set-Reset Capability
• Static Flip-Flop Operation - Retains State Indefinitely
With Clock Level Either “High” Or “Low”
• Medium-Speed Operation - 16 MHz (typ.) Clock Toggle
Rate at 10V
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25^oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Registers
• Counters
• Control Circuits
Q1 1
Q1 2
CLOCK 1 3
RESET 1 4
D1 5
SET 1 6
VSS 7
Functional Diagram
6
SET 1
5
D1
3
CLOCK 1
4
RESET 1
8
SET 2
9
D2
11
CLOCK 2
14 VDD
13 Q2
12 Q2
11 CLOCK 2
10 RESET 2
9 D2
8 SET 2
VDD
14
F/F1
2
Q1
1
Q1
F/F2
12
Q2
13
Q2
Description
CD4013BMS consists of two identical, independent data
type flip-flops. Each flip-flop has independent data, set,
reset, and clock inputs and Q and Q outputs. These devices
can be used for shift register applications, and, by
connecting Q output to the data input, for counter and toggle
applications. The logic level present at the D input is
transferred to the Q output during the positive going
transition of the clock pulse. Setting or resetting is
independent of the clock and is accomplished by a high level
on the set or reset line, respectively.
The CD4013BMS is supplied in these 14 lead outline pack-
ages:
10
RESET 2
7
VSS
Braze Seal DIP H4Q
Frit Seal DIP
H1B
Ceramic Flatpack H3W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
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File Number 3080