CD4007UBMS Datasheet, PDF (6/9 Pages) Intersil Corporation – CMOS Dual Complementary Pair Plus Inverter

CD4007UBMS
Logic Circuits
6
8
3
5
10
12
(14, 2, 11); (8, 13);
(1, 5); (7, 4, 9)
a) TRIPLE INVERTERS
6
3
12
10
(13, 2); (1, 11);
(12, 5, 8); (7, 4, 9)
b) 3 - INPUT NOR GATE
6
3
12
10
(1, 12, 13); (2, 14, 11);
(4, 8); (5, 9)
c) 3 - INPUT NAND GATE
V_DD
#
V_DD
B 10
A3
C6
#ALL P- UNIT SUBSTRATES
ARE CONNECTED TO V_DD
ALL N- UNIT SUBSTRATES
ARE CONNECTED TO V_SS
OUT
12
V_SS
A
B
A
C
C
OUT
B OUT (VDD) = C + AB
OUT (VSS) = CA + CB
V_SS
(13, 12, 5); (4, 9, 8);
(14, 2); (1, 11)
d) TREE (RELAY) LOGIC
VDD (OPTIONAL VDD PULL-UP)
VDD
12
6
(6, 3, 10); (8, 5, 12);
(11, 14); (7, 4, 9)
VSS
e) HIGH SINK-CURRENT DRIVER
VDD
12
6
(6, 3, 10); (13, 1, 12);
(14, 2, 11); (7, 9)
6
12
(OPTIONAL VSS PULL-DOWN)
VSS
f) HIGH SOURCE-CURRENT DRIVER
6
CLOCK
IN
(OUT)
12
2
OUT1
(IN1)
TG1
TG2
4
OUT2
(IN2)
(6, 3, 10); (14, 2, 11);
(7, 4, 9); (13, 8, 1, 5, 12)
VSS
(1, 5, 12); (2, 9);
(11, 4); (8, 13, 10);
(6, 3)
g) HIGH SINK - AND SOURCE-CURRENT DRIVER
h) DUAL BI-DIRECTIONAL TRANSMISSION GATING
FIGURE 2. SAMPLE CMOS LOGIC CIRCUIT ARRANGEMENTS USING TYPE CD4007UBMS
7-671