CD4007UBMS Datasheet, PDF (1/9 Pages) Intersil Corporation – CMOS Dual Complementary Pair Plus Inverter

CD4007UBMS
November 1994
CMOS Dual Complementary Pair Plus Inverter
Features
Pinout
• High-Voltage Type (20V Rating)
• Standardized Symmetrical Output Characteristics
• Medium Speed Operation
- tPHL, tPLH = 30 ns (typ) at 10V
• 100% Tested for Maximum Quiescent Current at 20V
• Meets All Requirements of JEDEC Tentative Stan-
dards No. 13B, “Standard Specifications for Descrip-
tion of “B” Series CMOS Devices”
• Maximum Input Current of 1µA at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and +25^oC
Applications
Q2 (P) DRAIN 1
Q2 (P) SOURCE 2
Q2 GATES 3
Q2 (N) SOURCE 4
Q2 (N) DRAIN 5
Q1 GATES 6
VSS, Q1, Q2, Q3 (N) 7
SUBSTRATES Q1 (N)
SOURCE
CD4007UBMS
TOP VIEW
14 VDD, Q1, Q2, Q3 (P)
SUBSTRATES, Q1(P) DRAIN
13 Q1 (P) SOURCE
12 Q3 (N) DRAIN, Q3 (P) SOURCE
11 Q3 (P) DRAIN
10 Q3 GATES
9 Q3 (N) SOURCE
8 Q1 (N) DRAIN
• Extremely High-Input Impedance Amplifiers
• Shapers
• Inverters
• Threshold Detector
• Linear Amplifiers
• Crystal Oscillators
Description
CD4007BMS types are comprised of three n-channel and
three p-channel enhancement-type MOS transistors. The
transistor elements are accessible through the package ter-
minals to provide a convenient means for constructing the
various typical circuits as shown in Figure 2.
More complex functions are possible using multiple pack-
ages. Numbers shown in parentheses indicate terminals that
are connected together to form the various configurations
listed.
The CD4007BMS is supplied in these 14 lead outline pack-
ages:
Functional Diagram
14
2
11
p
p
p
6 ¹³³
1 ₁₀
12
8
5
n
n
n
7
4
9
TERMINAL NO. 14 - VDD
TERMINAL NO. 7 - VSS
Braze Seal DIP H4Q
Frit Seal DIP
H1B
Ceramic Flatpack H3W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-666
File Number 3291