CD4007UBMS Datasheet, PDF (5/9 Pages) Intersil Corporation – CMOS Dual Complementary Pair Plus Inverter

Specifications CD4007UBMS
TABLE 6. APPLICABLE SUBGROUPS (Continued)
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In
1 Note 1
1, 5, 8, 12, 13
3, 4, 6, 7, 9, 10
2, 11, 14
Static Burn-In
2 Note 1
1, 5, 8, 12, 13
4, 7, 9
2, 3, 6, 10, 11, 14
Dynamic Burn-
-
In Note 1
4, 7, 9
2, 11, 14
1, 5, 8, 12, 13
3, 6, 10
-
Irradiation
Note 2
1, 5, 8, 12, 13
4, 7, 9
2, 3, 6, 10, 11, 14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ±5%, VDD = 18V ±0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ±0.5V
Schematic Diagram
14
2 _**
11 _**
D2
D2
D2
*
D2
*
D2
*
D2
6
R1 D2 _** 13
D2
Q1 3
R1 D2 _** 1
D2
Q2 10
R1 D2
D1 D1
8
D1
D1 D1
5
D1
D1 D1
D2
D1
12 Q3
D1 ^**
*CMOS INPUT
D1
D1
D1
PROTECTION
NETWORK
**CMOS OUTPUT PROTECTION
NETWORK BETWEEN TERMINAL
NOS. 1, 2, 4, 5, 8, 9, 11, 12, 13
AND THE CORRESPONDING
DRAINS AND/OR SOURCES
7
V_DD
4 ^** PARASITIC AND
9 ^**
NETWORK COMPONENTS
D1 = N+ TO P WELL
R2
D2
OUTPUT
TERMINAL
D2 = P+ TO SUBSTRATE
R1 = 1 - 5 KΩ
R2 = 15 - 30Ω
D1
D1
V_SS
FIGURE 1. DETAILED SCHEMATIC DIAGRAM OF CD4007UBMS SHOWING INPUT, OUTPUT, AND PARASITIC DIODES
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