CD4006BMS Datasheet, PDF (6/8 Pages) Intersil Corporation – CMOS 18-Stage Static Register

CD4006BMS
Logic Diagram and Truth Table
CL
CL
p
p
D TG
TG
n
n
CL
CL
CL
p
TG
n
Q
D+1
CL
p
TG
Q
Q
n
CL
CL
OUT IF
4th OR 5th
STAGE
LOGIC DIAGRAM AND TRUTH TABLE (ONE REGISTER STAGE)
TRUTH TABEL FOR SHIFT REGISTER STAGE
D
CL*
D+1
0
0
1
1
X
NC
TRUTH TABLE FOR OUTPUT FROM TERM 2
D1 + 4
CL*
D1 + 4’
0
0
1
1
X
NC
1 = HIGH
0 = LOW
NC= NO CHANGE
X = DON’T CARE
* = LEVEL CHANGE
CLOCK
D1 + 4
D1
DQ
DQ
DQ
D
LATCH
D1 + 4’
CL
CL
CL
CL Q
CL
CL
CL
CL
CL
CL
CL
CL TO 14 MORE STAGES
D2
DQ
DQ
D
2 STAGES
CL
CL Q
CL Q
CL
CL
CL
D3
DQ
D
2 STAGES
CL
CL Q
CL
CL
D4
DQ
DQ
D
2 STAGES
CL
CL Q
CL Q
CL
CL
CL
D1 + 4
LATCH
CL
CL
CL
Q
p
= ^{D1 + 4 n}
CL
DETAILED LOGIC OF LATCH
CL
p
n
CL Q
LOGIC DIAGRAM WITH DETAIL OF LATCH
D2 + 5
D2 + 4
D3 + 4
D4 + 5
D4 + 4
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