CD4006BMS Datasheet, PDF (1/8 Pages) Intersil Corporation – CMOS 18-Stage Static Register

CD4006BMS
December 1992
CMOS 18-Stage Static Register
Features
Pinout
• High-Voltage Type (20V Rating)
• Fully Static Operation
• Shifting Rates Up to 12MHz at 10V (typ)
• Permanent Register Storage with Clock Line High or
Low - No Information Recirculation Required
• 100% Tested for Quiescent Current at 20V
• Standardized, Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and +25^oC
• Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Stan-
dards No. 13B, “Standard Specifications for Descrip-
tion of “B” Series CMOS Devices”
CD4006BM
TOP VIEW
D1 1
D1 + 4’ 2
CLOCK 3
D2 4
D3 5
D4 6
VSS 7
14 VDD
13 D1 + 4
12 D2 + 5
11 D2 + 4
10 D3 + 4
9 D4 + 5
8 D4 + 4
Functional Diagram
VDD
14
Applications
• Serial Shift Registers
• Frequency Division
• Time Delay Circuits
Description
CD4006BMS types are composed of 4 separate shift register
sections: two sections of four stages and two sections of five
stages with an output tap at the fourth stage. Each section has
an independent single-rail data path.
A common clock signal is used for all stages. Data are shifted
to the next stages on negative-going transitions of the clock.
Through appropriate connections of inputs and outputs, multi-
ple register sections of 4, 5, 8, and 9 stages or single register
sections of 10, 12, 13, 14, 16, 17 and 18 stages can be imple-
mented using one CD4006BMS package. Longer shift register
sections can be assembled by using more than one
CD4006BMS.
To facilitate cascading stages when clock rise and fall times are
slow, an optional output (D1 + 4’) that is delayed one-half clock-
cycle, is provided (see Truth Table for Output from Term. 2).
The CD4006BMS is supplied in these 14 lead outline pack-
ages:
Braze Seal DIP H4Q
Frit Seal DIP
H6D
Ceramic Flatpack H4F
1
D1
4
STAGE
4
D2
3
CLOCK
5
D3
4
STAGE
4
STAGE
6
D4
4
STAGE
LATCH
1
STAGE
13
D1 + 4
2
D1 + 4’
12
D2 + 5
11
10 ^{D2 + 4}
D3 + 4
1
STAGE
9
D4 + 5
8
D4 + 4
7
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-658
File Number 3290