82C88 Datasheet, PDF (6/10 Pages) Intersil Corporation – CMOS Bus Controller

82C88
AC Electrical Specifications
V_CC = 5.0V ± 10%;
T_A
T_A
T_A
=
=
=
0^oC to +70^oC (C82C88);
-40^oC to +85^oC (I82C88);
-55^oC to +125^oC (M82C88)
8MHz
10MHz
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
TIMING REQUIREMENTS
(1) TCLCL CLK Cycle Period
125
-
100
-
(2) TCLCH CLK Low Time
55
-
50
-
(3) TCHCL CLK High Time
40
-
37
-
(4) TSVCH Status Active Setup Time
35
-
35
-
(5) TCHSV Status Inactive Hold Time
10
-
10
-
(6) TSHCL Status Inactive Setup Time
35
-
35
-
(7) TCLSH Status Active Hold Time
10
-
10
-
TIMING RESPONSES
(8) TCVNV Control Active Delay
5
45
5
45
(9) TCVNX Control Inactive Delay
10
45
10
45
(10) TCLLH ALE Active Delay (from CLK)
-
20
-
20
(11) TCLMCH MCE Active Delay (from CLK)
-
25
-
23
(12) TSVLH ALE Active Delay (from Status)
-
20
-
20
(13) TSVMCH MCE Active Delay (from Status)
-
30
-
23
(14) TCHLL ALE Inactive Delay
4
18
4
18
(15) TCLML Command Active Delay
5
35
5
35
(16) TCLMH Command Inactive Delay
5
35
5
35
(17) TCHDTL Direction Control Active Delay
-
50
-
50
(18) TCHDTH Direction Control Inactive Delay
-
30
-
30
(19) TAELCH Command Enable Time (Note 1) -
40
-
40
(20) TAEHCZ Command Disable Time
(Note 2)
-
40
-
40
(21) TAELCV Enable Delay Time
110
250
110
250
(22) TAEVNV AEN to DEN
-
25
-
25
(23) TCEVNV CEN to DEN, PDEN
-
25
-
25
(24) TCELRH CEN to Command
-
TCLML
-
TCLML
+10
(25) TLHLL ALE High Time
TCLCH - - TCLCH - -
10
10
NOTES:
1. TAELCH measurement is between 1.5V and 2.5V.
2. TAEHCZ measured at 0.5V change in VOUT.
12MHz
MIN
MAX
83
-
34
-
34
-
35
-
5
-
35
-
5
-
5
45
10
35
-
20
-
23
-
20
-
23
4
18
5
35
5
35
-
50
-
30
-
40
-
40
110
250
-
25
-
25
-
TCLML
TCLCH - n
10
TEST
UNITS CONDITIONS
ns
ns
ns
ns
ns
ns
ns
ns
1
ns
1
ns
1
ns
1
ns
1
ns
1
ns
1
ns
2
ns
2
ns
1
ns
1
ns
3
ns
4
ns
2
ns
1
ns
1
ns
2
ns
1
AC Testing Input, Output Waveform
INPUT
V_IH +0.4V
1.5V
V_IL -0.4V
OUTPUT
V_OH
1.5V
V_OL
A.C. Testing: All input signals (other than CLK) must switch
between V_IL -0.4V and V_IH +0.4. CLK must switch between 0.4V
and V_CC -0.4V. Input rise and fall times are driven at 1ns/V.
A.C. Test Circuit
V1
OUTPUT FROM
DEVICE
UNDER TEST
NOTE:
INCLUDES STRAY AND JIG CAPACITANCE
R1
TEST
POINT
C1 (SEE NOTE)
TABLE 2. TEST CONDITION DEFINITION TABLE
TEST CONDITION
1
2
3
4
V1
2.13V
2.29V
1.5V
1.5V
R1
220Ω
91Ω
187Ω
187Ω
C1
80pF
300pF
300pF
50pF
4-338