X9430 Datasheet, PDF (5/21 Pages) Xicor Inc. – Dual Digitally Controlled Potentiometer (XDCP™) with Operational Amplifier

X9430
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A₀ - A₁ input
pins. The X9430 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9430 to successfully
continue the command sequence. The A₀ - A₁ inputs
can be actively driven by CMOS input signals or tied to
V_CC or V_SS.
The remaining two bits in the slave byte must be set to 0.
Figure 1. Identification Byte Format
Device Type
Identifier
0 1 0 1 0 0 A1 A0
Device Address
Instruction Byte
The next byte sent to the X9430 contains the instruc-
tion and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the WCRs of the two pots, and when
applicable, they point to one of four associated data
registers. The format is shown below in Figure 2.
Figure 2. Instruction Byte Format
Register
Select
I3 I2 I1 I0 R1 R0 0 P0
Instructions
WCR Select
The four high order bits of the instruction byte specify
the operation. The next two bits (R₁ and R₀) select one
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last bit (P₀)
selects which one of the two potentiometers is to be
affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
The basic sequence of the two byte instructions is
illustrated in Figure 3. These two-byte instructions
exchange data between a wiper counter register and
one of the four data registers associated with each. A
transfer from a data register to a wiper counter register
is essentially a write to a static RAM. The response of
the wiper to this action will be delayed t_WRL. A transfer
from the wiper counter register (current wiper position)
to a data register is a write to nonvolatile memory and
takes a minimum of t_WR to complete. The transfer can
occur between one of the two potentiometers and one
of its associated registers; or it may occur globally,
wherein the transfer occurs between both of the poten-
tiometers and one of their associated registers.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9430; either between the host and
one of the data registers or directly between the host
and the Wiper Counter and Registers. These instruc-
tions are: 1) Read Wiper Counter Register, read the
current wiper position of the selected pot 2) Write
Wiper Counter Register, i.e. change current wiper
position of the selected pot; 3) Read Data Register,
read the contents of the selected nonvolatile register; 4)
Write Data Register, write a new value to the selected
data register; 5)Read Status, returns the contents of the
WIP bit which indicates if an internal write cycle is in
progress.
The sequence of these operations is shown in Figure
4 and Figure 5.
The final command is Increment/Decrement. It is differ-
ent from the other commands, because it’s length is
indeterminate. Once the command is issued, the master
can clock the selected wiper up and/or down in one resis-
tor segment steps; thereby, providing a fine tuning capa-
bility to the host. For each SCK clock pulse (t_HIGH) while
SI is HIGH, the selected wiper will move one resistor
segment towards the V_H terminal. Similarly, for each
SCK clock pulse while SI is LOW, the selected wiper will
move one resistor segment towards the V_L terminal. A
detailed illustration of the sequence and timing for this
operation are shown in Figure 6 and Figure 7.
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FN8198.0
March 11, 2005