X60250 Datasheet, PDF (5/16 Pages) Intersil Corporation – Micro Power Programmable Voltage Reference

X60250
A.C. TEST CONDITIONS
Input Pulse Levels
Input rise and fall times
Input and output timing threshold level
External load at pin SDA
V_CC x 0.1 to V_CC x 0.9
10ns
V_CC x 0.5
2.3kΩ to V_CC and 100 pF to V_SS
AC SPECIFICATIONS
Symbol
f_SCL
t_IN
t_AA
t_BUF
t_LOW
t_HIGH
t_SU:STA
t_HD:STA
t_SU:DAT
t_HD:DAT
t_SU:STO
t_DH
t_R
t_F
Cb
Parameter
SCL Clock Frequency
Pulse width Suppression Time at inputs ⁽²⁾
SCL LOW to SDA Data Out Valid ⁽²⁾
Time the bus must be free before a new transmission can start ⁽²⁾
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time ⁽²⁾
Data Output Hold Time ⁽²⁾
SDA and SCL Rise Time ^{(2, 3)}
SDA and SCL Fall Time ^{(2, 3)}
Capacitive load for each bus line ^{(2, 3)}
Min.
0
50
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb
20 +.1Cb
Max.
400
0.9
300
300
400
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
pF
TIMING DIAGRAMS
Bus Timing
t_BUF
t_F
SCL
t_SU:STA
SDA IN
t_SU:DAT
t_HD:STA
t_HIGH
t_LOW
t_HD:DAT
SDA OUT
t_R
t_SU:STO
t_AA t_DH
t_BUF
t_HD:STO
t_HD:DAT
5
FN8146.1
September 14, 2005