X60250 Datasheet, PDF (12/16 Pages) Intersil Corporation – Micro Power Programmable Voltage Reference

X60250
Figure 6. Byte Write Sequence
Signals from
the Master
SDA Bus
Signals From
The Slave
S
t _Device
a
r ^ID
t
Slave
Address*
Byte
Address 0
S
t
Data
o
p
0 1 0 1 0 0 0/1 0
A
C
K
A
A
C
C
K
K
*Note: The X60250 will respond to either 000 or 001 slave addresses.
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array.
Upon receipt of each address byte, the X60250 responds
with an acknowledge. After receiving the address bytes
the X60250 awaits the eight bits of data. After receiving
the 8 data bits, the X60250 again responds with an
acknowledge. The master then terminates the transfer by
generating a stop condition. The X60250 then begins an
internal write cycle of the data to the nonvolatile memory.
During the internal write cycle, the device inputs are
disabled, so the device will not respond to any requests
from the master. The SDA output is at high impedance.
See Figure 6.
Figure 7. Random Address Read Sequence
A write to a protected block of memory is ignored, but will
still receive an acknowledge. At the end of the write
command, the X60250 will not initiate an internal write
cycle, and will continue to okay commands.
Stops and Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
and its associated ACK signal. If a stop is issued in the
middle of a data byte, or before 1 full data byte + ACK is
sent, then the X60250 resets itself without performing the
write. The contents of the array are not affected.
Signals from the
S
t
Master a
r
Device Slave
ID
Address
S
Byte
t Device Slave
Address 0 ^a
r
ID
Address
S
t
o
t
t
p
SDA Bus
0 1 0 1 0 0 0/1 0
01 0 1 0 0 0 1
Signals from
the Slave
A
A
C
C
K
K
A
C
K
Data
Random Address Read
Random read operation allows the master to access any
location in the X60250. Prior to issuing the Slave
Address Byte, the master must first perform a “dummy”
write operation.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues the
word address bytes. After acknowledging receipt of each
word address byte, the master immediately issues
another start condition and the slave address byte. This
is followed by an acknowledge from the device and then
by the eight bit data word. The master terminates the
read operation by not responding with an acknowledge
and then issuing a stop condition. Refer to Figure 7 for
the address, acknowledge, and data transfer sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of the
second start shown in Figure 7. The X60250 then goes
into standby mode after the stop and all bus activity will
be ignored until a start is detected. This operation loads
the new address into the address counter. The next
Current Address Read operation will read from the newly
loaded address. This operation could be useful if the
master knows the next address it needs to read, but is
not ready for the data.
12
FN8146.1
September 14, 2005