X1243 Datasheet, PDF (5/17 Pages) Xicor Inc. – Real Time Clock/Calendar/Alarm with EEPROM

X1243
24-Hour Time
If the T24 bit of the HR register is 1, the RTC will use a 24-
hour format. If the T24 bit is 0, the RTC will use 12-hour
format and bit H21 will function as an AM/PM indicator with a
‘1’ representing PM. The clock defaults to Standard Time
with H21 = 0.
Leap Years
Leap years add the day February 29 and are dened as those
years that are divisible by 4.Years divisible by 100 are not
leap years, unless they are also divisible by 400. This means
that the year 2000 is a leap year, the year 2100 is not. The
X1243 does not correct for the leap year in the year 2100.
Status Register (SR)
The Status Register is located in the RTC area at address
003FH. This is a volatile register only and is used to control
the WEL and RWEL write enable latches, read an optional
Low Voltage Sense bit, and read the two alarm bits. This
register is logically sepa-rated from both the array and the
Clock/Control Regis-ters (CCR).
ADDR
003Fh
Default
TABLE 2. STATUS REGISTER (SR)
7
6
5 43 2
1
BAT AL1 AL0 0 0 RWE WEL
L
0
0
0 00 0
0
0
RTCF
1
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating from
V_BACK, not V_CC. It is a read only bit and is set/ reset by
hardware.
AL1, AL0: Alarm Bits (Volatile)
These bits announce if either alarm 1 or alarm 2 match the
real time clock. If there is a match, the respective bit is set to
‘1’. The falling edge of the last data bit in a SR Read
operation resets the ags.
NOTE: Only the AL bits that are set when an SR read starts will be
reset. An alarm bit that is set by an alarm occurring during an SR read
operation will remain set after the read operation is complete.
RWEL: Register Write Enable Latch (Volatile)
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior to any
writes to the Clock/Control Registers. Writes to RWEL bit do
not cause a nonvolatile write cycle, so the device is ready for
the next operation immediately after the stop condition. A
write to the CCR requires both the RWEL and WEL bits to be
set in a specic sequence.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the CCR and mem-ory
array during a write operation. This bit is a volatile latch that
powers up in the LOW (disabled) state. While the WEL bit is
LOW, writes to the CCR or any array address will be ignored
(no acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and zeroes to
the other bits of the Sta-tus Register. Once set, WEL
remains set until either reset to 0 (by writing a “0” to the WEL
bit and zeroes to the other bits of the Status Register) or until
the part powers up again. Writes to WEL bit do not cause a
nonvolatile write cycle, so the device is ready for the next
operation immediately after the stop condition.
RTCF: Real Time Clock Fail Bit (Volatile)
This bit is set to a ‘1’ after a total power failure. This is a read
only bit that is set by hardware when the device powers up
after having lost all power to the device. The bit is set
regardless of whether V or V is applied rst. The loss
CC
BACK
of one or the other supplies does not result in setting the
RTCF bit. The rst valid write to the RTC (writing one byte is
sufcient) resets the RTCF bit to ‘0’.
Unused Bits
These devices do not use bits 3 or 4, but must have a zero in
these bit positions. The Data Byte output during a SR read
will contain zeros in these bit locations.
Control Registers
Block Protect Bits—BP2, BP1, BP0 (Nonvolatile)
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected
block of memory is ignored. The block pro-tect bits will
prevent write operations to one of eight segments of the
array. The partitions are described in Table 3.
TABLE 3. BLOCK PROTECT BITS
BP2 BP1 BP0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
PROTECTED
ADDRESSES X1243
None
600h - 7FFh
400h - 7FFh
000h - 7FFh
000h - 03Fh
000h - 07Fh
000h - 0FFh
000h - 1FFh
ARRAY
LOCK
None
Upper 1/4
Upper 1/2
Full Array
First Page
First 2 pgs
First 4 pgs
First 8 pgs
Interrupt Control Bits (AL1E, AL0E)
There are two Interrupt Control bits, Alarm 1 Interrupt Enable
(AL1E) and Alarm 0 Interrupt Enable (AL0E) to specically
enable or disable the alarm interrupt signal output. The
interrupt output is enabled when either bit is set to ‘1’. Two
volatile bits (AL1 and AL0), associated with these alarms,
indicate if an alarm has happened. These bits are set on an
alarm condition regardless of whether the alarm interrupts are
enabled. The AL1 and AL0 bits are reset by the falling edge of
the 8th clock of a read of the register containing the bits.
5
FN8249.0
April 28, 2005