X1243 Datasheet, PDF (10/17 Pages) Xicor Inc. – Real Time Clock/Calendar/Alarm with EEPROM

X1243
S
Signals from
the Master
t
Slave
a
r
Address
S
t
o
t
p
SDA Bus
1
1 1 11
Signals from
the Slave
A
C
K
Data
FIGURE 10. CURRENT ADDRESS READ SEQUENCE
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a stop condi-tion during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a stop condition.
Random Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must rst
perform a “dummy” write operation.
The master issues the start condition and the Slave Address
Byte, receives an acknowledge, then issues the Word
Address Bytes. After acknowledging receipts of the Word
Address Bytes, the master immediately issues another start
condition and the Slave Address Byte with the R/W bit set to
one. This is followed by an acknowledge from the device and
then by the eight bit word. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition. Refer to Figure 11 for the address,
acknowledge, and data transfer sequence.
In a similar operation, called “Set Current Address,” the
device sets the address if a stop is issued instead of the
second start shown in Figure 11. The X1243 then goes into
standby mode after the stop and all bus activity will be
ignored until a start is detected. This operation loads the new
address into the address counter. The next Cur-rent Address
Read operation will read from the newly loaded address.
This operation could be useful if the master knows the next
address it needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current address
read or random address read. The rst Data Byte is
transmitted as with the other modes; however, the master
now responds with an acknowledge, indicat-ing it requires
additional data. The device continues to output data for each
acknowledge received. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition.
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address
counter for read operations increments through all page and
column addresses, allowing the entire memory contents to
be serially read during one operation. At the end of the
address space the counter “rolls over” to the start of the
address space and the device continues to output data for
each acknowledge received. Refer to Figure 12 for the
acknowledge and data transfer sequence.
S
Signals from
the Master
t
a
Slave
r
t
Address
Word
Address 1
Word
Address 0
S
t
Slave
a
r
Address
t
S
t
o
p
SDA Bus
1
1 1 11 0 0 00 0
1
111 1
Signals from
the Slave
A
A
A
C
C
C
K
K
K
A
C
K
Data
FIGURE 11. RANDOM ADDRESS READ
10
FN8249.0
April 28, 2005