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X1243 Datasheet, PDF (1/17 Pages) Xicor Inc. – Real Time Clock/Calendar/Alarm with EEPROM
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Real Time Clock/Calendar/Alarm with
EEPROM
Features
• 2 alarms—interrupt output
- Settable on the second, 10s of seconds, minute, 10s of
minutes, hour, day, month, or day of the week
- Repeat alarm for time base generation
• 2-wire interface interoperable with I2C
- 400kHz data transfer rate
• Secondary power supply input with internal switch-over
circuitry
• 2Kbytes of EEPROM
- 64-byte page write mode
- 3-bit Block Lock™ protection
• Low power CMOS
- <1µA operating current
- <3mA active current during program
- <400µA active current during data read
• Single byte write capability
• Typical nonvolatile write cycle time: 5ms
• High reliability
• Small package options
- 8-lead SOIC package, 8-lead TSSOP package
Block Diagram
X1
32.768kHz
X2
Oscillator
X1243
16K (2K x 8), 2-Wire RTC
April 28, 2005
FN8249.0
Description
The X1243 is a Real Time Clock with clock/calendar circuits
and two alarms. The dual port clock and alarm registers
allow the clock to operate, without loss of accuracy, even
during read and write operations.
The clock/calendar provides functionality that is con-trollable
and readable through a set of registers. The clock, using a
low cost 32.768kHz crystal input, accu-rately tracks the time
in seconds, minutes, hours, date, day, month and years. It
has leap year correction and automatic adjustment for
months with less than 31 days.
An alarm match of the RTC sets an interrupt ag and
activates an interrupt pin. An alternative alarm function
provides a pulsed interrupt for long time constant time-
bases.
The device offers a backup power input pin. This VBACK pin
allows the device to be backed up by a non-rechargeable
battery. The RTC is fully operational from 1.8 to 5.5 volts.
The X1243 provides a 2Kbyte EEPROM array, giving a safe,
secure memory for critical user and conguration data. This
memory is unaffected by complete failure of the main and
backup supplies.
Frequency 1Hz
Divider
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
SCL
SDA
Serial
Interface
Decoder
IRQ
Control
Decode
Logic
8
Control
Registers
(EEPROM)
Status
Register
(SRAM)
Interrupt Enable
Alarm
Alarm
Compare
Alarm Regs
(EEPROM)
16k (2k x 8)
EEPROM
Array
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright Intersil Americas Inc. 2005. All Rights Reserved
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