ISL6719_14 Datasheet, PDF (5/9 Pages) Intersil Corporation – 100V Linear Bias Supply

ISL6719
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2
and “Typical Application” on page 3. 17V < VPWR < 100V, C_VSW = 1µF, I_VSW = -3mA, VSW Enabled, T_A = -40°C to +105°C (Note 7), Typical values are at
T_A = +25°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 8)
TYP
(Note 8)
UNITS
Source Voltage Headroom (VPWR - VSW) VSW = 20V, AUXIN = 0V
Minimum Required Load
I_VSW = -100mA
I_VSW = -50mA
6.2
V
5.2
V
-3
mA
Maximum VOUT, Faulted VSW_FB
VSW_FB = 0V, VPWR = 100V, AUXIN = 40V
21
25
V
Long Term Stability
T_A = +125°C, 1000 hours (Note 8),
VPWR = 48V, VSW = 10V, I_VSW = -10mA,
AUXIN = 15V
0.3
%
Operational Current (source)
VPWR = 48V, AUXIN = 17V, VSW = 15V
-100
mA
Current Limit
VPWR = 48V, AUXIN = 15V, VSW = 10V
-100
-230
-400
mA
VSW_FB Bias Current
VPWR = 100V, AUXIN = 40V, VSW = 10V,
-0.5
VSW_FB = 1.5V
1.5
µA
COMPA, COMPB Recommended
Capacitance
(Note 9)
170
220
270
pF
COMPA Voltage
0.7
V
COMPB Voltage
VSW + 5.0
V
ENABLE, ENABLE_N
High Level Input Voltage (VIH)
VPWR = 48V, AUXIN = 0V
2.5
3.0
3.6
V
Low Level Input Voltage (VIL)
VPWR = 48V, AUXIN = 0V
1.6
2.0
2.5
V
Hysteresis
VPWR = 48V, AUXIN = 0V
0.7
1.0
1.3
V
Pull-Up Resistance
Turn-On Delay
Turn-Off Delay
THERMAL PROTECTION
V_ENABLE = V_{N_ENABL} = 0V
-
100
-
kΩ
T_{VSW, 10%} - T_ENABLE, T_VSW,10% - T_{ENABLE_N,}
25
µs
I_VSW = -3mA
T_{VSW, 10%} - T_ENABLE, T_VSW,10% - T_{ENABLE_N,}
40
µs
I_VSW = -50mA
Thermal Shutdown
150
°C
Thermal Shutdown Clear
95
°C
Hysteresis
55
°C
NOTE:
7. Specifications at -40°C and +105°C are guaranteed by +25°C test with margin limits.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and
are not production tested.
9. Limits established by characterization and are not production tested.
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5
FN6555.2
July 15, 2014