ISL6131 Datasheet, PDF (5/13 Pages) Intersil Corporation – Multiple Voltage Supervisory ICs

ISL6131, ISL6132
Description and Operation
The ISL6131 is a four voltage high accuracy supervisory IC
designed to monitor multiple voltages greater than 0.7V
relative to PIN 10 of the IC.
Upon V_DD bias power up, the STATUS and PGOOD outputs
are held correctly low once V_DD is as low as 1V. Once
biased to 1.5V the IC continuously monitors from one to four
voltages independently through external resistor dividers
comparing each voltage monitoring (VMON) pin voltage to
an internal 0.633V (V_VMONvth) reference.
With the EN input driven high or open as each VMON input
rises above V_VMONvth a timer is set to ensure ~160ms of
continuous compliance then the related STATUS output is
released to be pulled high. The STATUS outputs are open-
drain to allow ORing of these signals and interfacing to a
logic high level up to V_DD. The STATUS are designed to
reject short transients (~30μs) on the VMON inputs. Once all
STATUS outputs are high a power good (PGOOD) output
signal is generated high to indicate all the monitored
voltages are greater than minimum compliance level.
Once any VMON input falls below V_VMONvth for longer than
the glitch filter time both the PGOOD and the related STATUS
output are pulled low. The other STATUS outputs will remain
high as long as their corresponding VMON voltage remains
valid and the PGOOD validation process is reset.
Figure 1 illustrates ISL6131 typical application schematic and
Figure 3 is an operational timing diagram. See Figures 10 to
17 for ISL6131 function and performance. Figures 10 and 11
show the V_DD rising along with STATUS and PGOOD
response. Figures 12 and 13 illustrate VMON falling below
V_VMONvth and Figure 14 illustrates VMON rising above
V_VMONvth with STATUS and PGOOD response. Figure 15
shows the V_DD failing with STATUS and PGOOD response.
Figures 16 and 17 illustrate ENABLE to STATUS and PGOOD
timing.
If less than four voltages are being monitored, connect the
unused VMON pins to V_DD for proper operation. All unused
STATUS outputs can be left open.
The ISL6132 is a dual voltage monitor for under and
overvoltage compliance. Figure 2 illustrates the typical
ISL6132 implementation schematic and Figure 4 is the
operational timing diagram.
There are 2 pairs of monitors each with an undervoltage
(UVMON) input and overvoltage (OVMON) input along with
with associated STATUS and PGOOD outputs.
Upon V_DD bias power up, the STATUS and PGOOD outputs
are held correctly low once V_DD is as low as 1V. Once
biased to 1.5V the IC continuously monitors the voltage
through external resistor dividers comparing each VMON pin
voltage to an internal 0.633V reference. At proper bias the
OVSTATUS are pulled high and the UVSTATUS and
PGOOD are pulled low. Once the UVMON input > the
VMON Vth continuously for ~160ms, its associated STATUS
output will release high indicating that the minimum voltage
condition has been met. As both UVMON and OVMON
inputs are satisfied the PGOOD output is released to go high
indicating that the monitored voltage is within the specified
window. Figure 18 illustrates this performance for a 4V to 5V
window.
When VMON does not satisfy its voltage high or low criteria
for more than the glitch filter time, the associated STATUS
and PGOOD are pulled low. Figures 19 and 20 illustrate this
performance for a 4V to 5V compliant window.
Figures 21-23 illustrate the VMON glitch filter timing to
STATUS and PGOOD notification and transient immunity.
The ENABLE input when pulled low allows for monitoring
and reporting function to be disabled. Figure 24 shows
ENABLE high to PGOOD timing for compliant voltage.
When choosing resistors for the divider remember to keep
the current through the string bounded by power loss
tolerance at the top end and noise immunity at the bottom
end. For most applications total divider resistance in the
10kΩ -100kΩ range is advisable with 1% tolerance resistors
being used to reduce monitoring error.
Referencing Figures 1 and 2, choosing the two resistor
values is straightforward for the ISL6131 as the ratio of
resistance should equal the ratio of the desired trip voltage
to the internal reference, 0.633V).
For the ISL6131, two dividers of two resistors each can be
employed to monitor the OV and UV levels for each voltage.
Otherwise, use a single three resistor string for each voltage.
In the three resistor divider string the ratio of the desired
over voltage trip point to the internal reference is equal to the
ratio of the two upper resistors to the lowest (GND
connected) resistor. The desired under voltage trip point
ratio to the internal reference voltage is equal to the ratio of
the uppermost (voltage connected) resistor to the lower two
resistors. An example follows;
1. Establish lower and upper trip level: 3.3V ±20% or 2.64V
(UV) and 3.96V (OV)
2. Establish total resistor string value: 10kΩ, Ir = divider current
3. (Rm+Rl)*Ir = 0.623V @ UV and Rl * Ir = 0.633V @ OV
4. Rm+Rl = 0.623V / Ir @ UV => Rm+Rl = 0.623V / (2.64V
/10kΩ) = 2.359kΩ
5. Rl = 0.633V / Ir @ OV => Rl = 0.633V /(3.96V/10kΩ) =
1.598kΩ
6. Rm = 2.359kΩ - 1.598kΩ = 0.761kΩ
7. Ru = 10kΩ - 2.397kΩ = 7.641kΩ
8. Choose standard value resistors that most closely
approximate these ideal values. Choosing a different total
divider resistance value may yield a more ideal ratio with
available resistors values.
5
FN9119.4
August 17, 2010