HD-6409 Datasheet, PDF (5/12 Pages) Intersil Corporation – CMOS Manchester Encoder-Decoder

HD-6409
There is a three bit delay between UDI, BOl, or BZI input and
the decoded NRZ data transmitted out of SDO.
Control of the decoder outputs is provided by the RST pin.
When RST is low, SDO, DCLK and NVM are forced low.
When RST is high, SDO is transmitted out synchronously
with the recovered clock DCLK. The NVM output remains
low after a low to high transition on RST until a valid sync
pattern is received.
The decoded data at SDO is in NRZ format. DCLK is pro-
vided so that the decoded bits can be shifted into an external
register on every high to low transition of this clock. Three bit
periods after an invalid Manchester bit is received on UDI, or
BOl, NVM goes low synchronously with the questionable
data output on SDO. FURTHER, THE DECODER DOES
NOT REESTABLISH PROPER DATA DECODING UNTIL
ANOTHER SYNC PATTERN IS RECOGNIZED.
DCLK
UDI
SDO
COMMAND
SYNC
1 00 10 101 0101 0
RST
NVM
FIGURE 2. DECODER OPERATION
Repeater Operation
Manchester Il data can be presented to the repeater in either
of two ways. The inputs Bipolar One In and Bipolar Zero In
will accept data from differential inputs such as a comparator
or sensed transformer coupled bus. The input Unipolar Data
In accepts only noninverted Manchester II coded data. The
decoder requires a single clock with a frequency 16X or 32X
the desired data rate. This clock is selected to 16X with
Speed Select low and 32X with Speed Select high. For long
data links the 32X mode should be used as this permits a
wider timing jitter margin.
The inputs UDl, or BOl, BZl are delayed approximately 1/2
bit period and repeated as outputs BOO and BZO. The 2X
ECLK is transmitted out of the repeater synchronously with
BOO and BZO.
A low on CTS enables ECLK, BOO, and BZO. In contrast to
the converter mode, a transition on CTS does not initiate a
synchronization sequence of eight 0’s and a command sync.
The repeater mode does recognize a command or data sync
pulse. SD/CDS is an output which reflects the state of the
most recent sync pulse received, with high indicating a com-
mand sync and low indicating a data sync.
When RST is low, the outputs SDO, DCLK, and NVM are
low, and SRST is set low. SRST remains low after RST goes
high and is not reset until a sync pulse and two valid
manchester bits are received with the reset bit low. The reset
bit is the first data bit after the sync pulse. With RST high,
NRZ Data is transmitted out of Serial Data Out synchro-
nously with the 1X DCLK.
INPUT
COUNT
1
2
3
4
5
6
7
ECLK
SYNC PULSE
UDI
BZO
BOO
RST
SRST
FIGURE 3. REPEATER OPERATION
5-5