HD-6409 Datasheet, PDF (4/12 Pages) Intersil Corporation – CMOS Manchester Encoder-Decoder

HD-6409
Pin Description
PIN
NUMBER TYPE SYMBOL
NAME
17
I
SS
Speed Select
18
O
BZO Bipolar Zero Output
19
O
BOO Bipolar One Out
20
I
V_CC V_CC
NOTE: (I) Input (O) Output
DESCRIPTION
A logic high on SS sets the data rate at 1/32 times the clock frequency while a
low sets the data rate at 1/16 times the clock frequency.
BZO and its logical complement BOO are the Manchester data outputs of the en-
coder. The inactive state for these outputs is in the high state.
See pin 18.
V_CC is the +5V power supply pin. A 0.1µF decoupling capacitor from V_CC (pin-
20) to GND (pin-10) is recommended.
Encoder Operation
The encoder uses free running clocks at 1X and 2X the data
rate derived from the system clock l_X for internal timing. CTS
is used to control the encoder outputs, ECLK, BOO and
BZO. A free running 1X ECLK is transmitted out of the
encoder to drive the external circuits which supply the NRZ
data to the MED at pin SD/CDS.
A low on CTS enables encoder outputs ECLK, BOO and
BZO, while a high on CTS forces BZO, BOO high and holds
ECLK low. When CTS goes from high to low 1 , a synchro-
nization sequence is transmitted out on BOO and BZO. A
synchronization sequence consists of eight Manchester “0”
bits followed by a command sync pulse. 2 A command
sync pulse is a 3-bit wide pulse with the first 1 1/2 bits high
followed by 1 1/2 bits low. 3 Serial NRZ data is clocked into
the encoder at SD/CDS on the high to low transition of ECLK
during the command sync pulse. The NRZ data received is
encoded into Manchester II data and transmitted out on
BOO and BZO following the command sync pulse. 4 Fol-
lowing the synchronization sequence, input data is encoded
and transmitted out continuously without parity check or
word framing. The length of the data block encoded is
defined by CTS. Manchester data out is inverted.
CTS
1
ECLK
SD/CDS
BZO
BOO
‘1’ ‘0’ ‘1’
‘1’ ‘0’ ‘1’
DON’T CARE
2 0 0 0 0 0 0 0 03
4
EIGHT “0’s”
COMMAND
SYNC
SYNCHRONIZATION SEQUENCE
t_CE6
t_CE5
FIGURE 1. ENCODER OPERATION
Decoder Operation
The decoder requires a single clock with a frequency 16X or
32X the desired data rate. The rate is selected on the speed
select with SS low producing a 16X clock and high a 32X
clock. For long data links the 32X mode should be used as
this permits a wider timing jitter margin. The internal opera-
tion of the decoder utilizes a free running clock synchronized
with incoming data for its clocking.
The Manchester II encoded data can be presented to the
decoder in either of two ways. The Bipolar One and Bipolar
Zero inputs will accept data from differential inputs such as a
comparator sensed transformer coupled bus. The Unipolar
Data input can only accept noninverted Manchester II
encoded data i.e. Bipolar One Out through an inverter to
Unipolar Data Input. The decoder continuously monitors this
data input for valid sync pattern. Note that while the MED
encoder section can generate only a command sync pattern,
the decoder can recognize either a command or data sync
pattern. A data sync is a logically inverted command sync.
5-4