82C54 Datasheet, PDF (5/17 Pages) Intel Corporation – CHMOS PROGRAMMABLE INTERVAL TIMER

82C54
Operational Description
General
After power-up, the state of the 82C54 is undefined. The
Mode, count value, and output of all Counters are undefined.
How each Counter operates is determined when it is pro-
grammed. Each Counter must be programmed before it can
be used. Unused counters need not be programmed.
Programming the 82C54
Counters are programmed by writing a Control Word and
then an initial count.
All Control Words are written into the Control Word Register,
which is selected when A1, A0 = 11. The Control Word spec-
ifies which Counter is being programmed.
By contrast, initial counts are written into the Counters, not
the Control Word Register. The A1, A0 inputs are used to
select the Counter to be written into. The format of the initial
count is determined by the Control Word used.
A1 A0
ADDRESS BUS (16)
CONTROL BUS
DATA BUS (8)
I/OR I/OW
8
A1 A0 CS
COUNTER
0
D0 - D7
82C54
COUNTER
1
RD WR
COUNTER
2
OUT GATE CLK OUT GATE CLK OUT GATE CLK
SC - Select Counter
SC1 SC0
0
0 Select Counter 0
0
1 Select Counter 1
1
0 Select Counter 2
1
1 Read-Back Command (See Read Operations)
RW - Read/Write
RW1 RW0
0 0 Counter Latch Command (See Read Operations)
0 1 Read/Write least significant byte only.
1 0 Read/Write most significant byte only.
1 1 Read/Write least significant byte first, then most
significant byte.
M - Mode
M2 M1
0
0
0
0
X
1
X
1
1
0
1
0
M0
0 Mode 0
1 Mode 1
0 Mode 2
1 Mode 3
0 Mode 4
1 Mode 5
BCD - Binary Coded Decimal
0 Binary Counter 16-bit
1 Binary Coded Decimal (BCD) Counter (4 Decades)
NOTE: Don’t Care bits (X) should be 0 to insure compatibility with
future products.
FIGURE 4. 82C54 SYSTEM INTERFACE
Possible Programming Sequence
Write Operations
The programming procedure for the 82C54 is very flexible.
Only two conventions need to be remembered:
1. For Each Counter, the Control Word must be written
before the initial count is written.
2. The initial count must follow the count format specified in the
Control Word (least significant byte only, most significant byte
only, or least significant byte and then most significant byte).
Since the Control Word Register and the three Counters have
separate addresses (selected by the A1, A0 inputs), and each
Control Word specifies the Counter it applies to (SC0, SC1 bits),
no special instruction sequence is required. Any programming
sequence that follows the conventions above is acceptable.
Control Word - Counter 0
LSB of Count - Counter 0
MSB of Count - Counter 0
Control Word - Counter 1
LSB of Count - Counter 1
MSB of Count - Counter 1
Control Word - Counter 2
LSB of Count - Counter 2
MSB of Count - Counter 2
Possible Programming Sequence
Control Word Format
A1, A0 = 11; CS = 0; RD = 1; WR = 0
Control Word - Counter 0
Control Word - Counter 1
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD
Control Word - Counter 2
LSB of Count - Counter 2
A1
A0
1
1
0
0
0
0
1
1
0
1
0
1
1
1
1
0
1
0
A1
A0
1
1
1
1
1
1
1
0
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