82C54 Datasheet, PDF (2/17 Pages) Intel Corporation – CHMOS PROGRAMMABLE INTERVAL TIMER

82C54
Ordering Information
8MHz
CP82C54
IP82C54
CS82C54
IS82C54
CD82C54
ID82C54
MD82C54/B
MR82C54/B
SMD # 8406501JA
SMD# 84065013A
CM82C54
PART NUMBERS
10MHz
CP82C54-10
IP82C54-10
CS82C54-10
IS82C54-10
CD82C54-10
ID82C54-10
MD82C54-10/B
MR82C54-10/B
-
-
CM82C54-10
Functional Diagram
12MHz
CP82C54-12
IP82C54-12
CS82C54-12
IS82C54-12
CD82C54-12
ID82C54-12
MD82C54-12/B
MR82C54-12/B
8406502JA
84065023A
CM82C54-12
TEMPERATURE
RANGE
0^oC to +70^oC
-40^oC to +85^oC
0^oC to +70^oC
-40^oC to +85^oC
0^oC to +70^oC
-40^oC to +85^oC
-55^oC to +125^oC
-55^oC to +125^oC
-55^oC to +125^oC
-55^oC to +125^oC
0^oC to +70^oC
PACKAGE
24 Lead PDIP
24 Lead PDIP
28 Lead PLCC
28 Lead PLCC
24 Lead CERDIP
24 Lead CERDIP
24 Lead CERDIP
28 Lead CLCC
24 Lead CERDIP
28 Lead CLCC
24 Lead SOIC
PKG. NO.
E24.6
E24.6
N28.45
N28.45
F24.6
F24.6
F24.6
J28.A
F24.6
J28.A
M24.3
D₇ - D₀ 8
DATA/
BUS
BUFFER
RD
WR
READ/
WRITE
A₀
LOGIC
A₁
CS
CONTROL
WORD
REGISTER
Pin Description
SYMBOL
D7 - D0
CLK 0
OUT 0
GATE 0
GND
OUT 1
GATE 1
CLK 1
GATE 2
OUT 2
DIP PIN
NUMBER
1-8
9
10
11
12
13
14
15
16
17
COUNTER
0
COUNTER
1
CLK 0
GATE 0
OUT 0
CONTROL
WORD
REGISTER
CLK 1
GATE 1
OUT 1
CONTROL
LOGIC
STATUS
LATCH
STATUS
REGISTER
INTERNAL BUS
CR_M
CR_L
CE
COUNTER
2
CLK 2
GATE 2
OUT 2
GATE n
CLK n OUT n
OL_M
OL_L
COUNTER INTERNAL BLOCK DIAGRAM
TYPE
I/O
I
O
I
O
I
I
I
O
DEFINITION
DATA: Bi-directional three-state data bus lines, connected to system data bus.
CLOCK 0: Clock input of Counter 0.
OUT 0: Output of Counter 0.
GATE 0: Gate input of Counter 0.
GROUND: Power supply connection.
OUT 1: Output of Counter 1.
GATE 1: Gate input of Counter 1.
CLOCK 1: Clock input of Counter 1.
GATE 2: Gate input of Counter 2.
OUT 2: Output of Counter 2.
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