X9525 Datasheet, PDF (4/26 Pages) Intersil Corporation – Fiber Channel/Gigabit Etherner Laser Diode Control for Fiber Optic Modules

X9525
SCL
from
1
Master
Data Output
from
Transmitter
8
9
Data Output
from
Receiver
Start
Acknowledge
Figure 3. Acknowledge Response From Receiver
minate further data transmissions if an ACKNOWLEDGE
is not detected. The master must then issue a STOP
condition to place the device into a known state.
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the X9525
can be split up into three main parts:
—Two Digitally Controlled Potentiometers (DCPs)
—EEPROM array
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed on
each of these individual parts, a 1, 2 or 3 Byte proto-
col is used. All operations however must begin with
the Slave Address Byte being issued on the SDA pin.
The Slave address selects the part of the X9525 to
be addressed, and specifies if a Read or Write opera-
tion is to be performed.
It should be noted that in order to perform a write opera-
tion to either a DCP or the EEPROM array, the Write
Enable Latch (WEL) bit must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 12.)
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
sists of four parts:
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9525.
—SA3 is the Physical Device Address bit, whose logic
level must match that of the corresponding A₀ pin in
order to enable communication to the X9525.
—The next two bits (SA2 - SA1) are the Internal Device
Address bits. Setting these bits to 00 internally selects
the EEPROM array, while setting these bits to 11
selects the DCP structures in the X9525. The CON-
STAT Register may be selected using the Internal
Device Address 10.
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA2 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
1 0 1 0 ^A₀
R/W
DEVICE TYPE
IDENTIFIER
PHYSICAL INTERNAL _{READ /}
DEVICE DEVICE _WRITE
ADDRESS ADDRESS
Internal Address
(SA2 - SA1)
00
10
11
Internally Addressed
Device
EEPROM Array
CONSTAT Register
DCP
Bit SA0
0
1
Operation
WRITE
READ
Figure 4. Slave Address Format
4
FN8210.0
March 10, 2005