X9525 Datasheet, PDF (14/26 Pages) Intersil Corporation – Fiber Channel/Gigabit Etherner Laser Diode Control for Fiber Optic Modules

X9525
Signals from
the Master
SDA Bus
Signals from
the Slave
S
WRITE Operation
S
t
t
READ Operation
S
t
a
r
Slave Address
Address Byte
a _{Slave Address}
r
o
p
t
t
10 1 0 0^A0 1 0 0 _{1 1 1 1 1 1 1 1}
A
A
C
C
K
K
1 0 1 0 0^A0 0 0 1
A
C
K
Data
“Dummy” Write
Figure 19. CONSTAT Register Read Command Sequence
For example, a sequence of writes to the device CON-
STAT register consisting of [02H, 06H, 02H] will reset the
BL0 and BL0 bits in the CONSTAT Register to “0”.
It should be noted that a write to any nonvolatile bit of
CONSTAT register will be ignored if the Write Protect pin
of the X9525 is active (HIGH) (See "WP: Write Protection
Pin").
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be read at
any time by performing a random read (See Figure 19).
Using the Slave Address Byte set to 1010A₀101, and an
Address Byte of FFh. Only one byte is read by each reg-
ister read operation. The X9525 resets itself after the first
byte is read. The master should supply a STOP condition
to be consistent with the bus protocol.
After setting the WEL and / or the RWEL bit(s) to a “1”, a
CONSTAT register read operation may occur, without
interrupting a proceeding CONSTAT register write oper-
ation.
When reading the contents of the CONSTAT register,
the bits CS7-CS5 and CS0 will always return “0”.
DATA PROTECTION
There are a number of levels of data protection features
designed into the X9525. Any write to the device first
requires setting of the WEL bit in the CONSTAT register.
A write to the CONSTAT register itself, further requires
the setting of the RWEL bit. Block Lock protection of the
device enables the user to inhibit writes to certain regions
of the EEPROM memory, as well as to all the DCPs. One
further level of data protection in the X9525, is incorpo-
rated in the form of the Write Protection pin.
WP: Write Protection Pin
When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X9525.
The table below (X9525 Write Permission Status) sum-
marizes the effect of the WP pin (and Block Lock), on the
write permission status of the device.
Additional Data Protection Features
In addition to the preceding features, the X9525 also
incorporates the following data protection functionality:
—The proper clock count and data bit sequence is
required prior to the STOP bit in order to start a nonvol-
atile write cycle.
X9525 Write Permission Status
Block Lock
Bits
DCP Volatile Write
BL0 BL1 WP
Permitted
x
1
1
NO
1
x
1
NO
0
0
1
YES
x
1
0
NO
1
x
0
NO
0
0
0
YES
DCP Nonvolatile
Write Permitted
NO
NO
NO
NO
NO
YES
Write to EEPROM
Permitted
NO
NO
NO
Not in locked region
Not in locked region
Yes (All Array)
Write to CONSTAT Register
Permitted
Volatile Bits Nonvolatile Bits
YES
NO
YES
NO
YES
NO
YES
YES
YES
YES
YES
YES
14
FN8210.0
March 10, 2005