X9525 Datasheet, PDF (10/26 Pages) Intersil Corporation – Fiber Channel/Gigabit Etherner Laser Diode Control for Fiber Optic Modules

X9525
7 bytes
5 b5ybteytses
address
= 6₁₀
address
11₁₀
address
15₁₀
address pointer
ends here
Addr = 7₁₀
Figure 13. Example: Writing 2 bytes to a 16-byte page starting at location 11.
Stops and EEPROM Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
and receiving the subsequent ACKNOWLEDGE signal.
If the master issues a STOP within a Data Byte, or before
the X9525 issues a corresponding ACKNOWLEDGE,
the X9525 cancels the write operation. Therefore, the
contents of the EEPROM array does not change.
EEPROM Array Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of the
Slave Address Byte is set to one. There are three basic
read operations: Current EEPROM Address Read, Ran-
dom EEPROM Read, and Sequential EEPROM Read.
Current EEPROM Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n + 1. On power-up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an ACKNOWLEDGE and
then transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond
with an ACKNOWLEDGE during the ninth clock and then
issues a STOP condition (See Figure 14 for the address,
ACKNOWLEDGE, and data transfer sequence).
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read oper-
ation, the master must either issue a STOP condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a STOP condition.
Another important point to note regarding the “Current
EEPROM Address Read” , is that this operation is not
available if the last executed operation was an access to
a DCP or the CONSTAT Register (i.e.: an operation
using the Device Type Identifier 1010A₀11 or
1010A₀10). Immediately after an operation to a DCP or
CONSTAT Register is performed, only a “Random
EEPROM Read” is available. Immediately following a
“Random EEPROM Read” , a “Current EEPROM
Address Read” or “Sequential EEPROM Read” is once
again available (assuming that no access to a DCP or
CONSTAT Register occur in the interim).
S
Signals from _t
S
the Master
a
Slave
t
r Address
o
t
p
SDA Bus
Signals from
the Slave
1
0
1
0
A
0
0
0
1
A
C
K
Data
Figure 14. Current EEPROM Address Read Sequence
10
FN8210.0
March 10, 2005