X5328 Datasheet, PDF (4/21 Pages) Intersil Corporation – CPU Supervisor with 32Kbit SPI EEPROM

X5328, X5329
PIN DESCRIPTION
Pin
Pin
(SOIC/PDIP) TSSOP
1
1
2
2
5
8
6
9
3
6
4
7
8
14
7
13
3-5,10-12
Name
CS
SO
SI
SCK
WP
V_SS
V_CC
RESET/
RESET
NC
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the device
will be in the standby power mode. CS LOW enables the device, placing it in the
active power mode. Prior to the start of any operation after power-up, a HIGH to
LOW transition on CS is required.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock. The Serial Clock controls the serial bus timing for data input and out-
put. The rising edge of SCK latches in the opcode, address, or data bits present on
the SI pin. The falling edge of SCK changes the data output on the SO pin.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the Watchdog Timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output
which goes active whenever V_CC falls below the minimum V_CC sense level. It
will remain active until V_CC rises above the minimum V_CC sense level for 200ms.
RESET/RESET goes active on power-up at about 1V and remains active for
200ms after the power supply stabilizes.
No internal connections
PIN CONFIGURATION
CS
SO
WP
V_CC
8 Ld SOIC/PDIP
1
8
2
7
X5328/29
3
6
4
5
V_CC
RESET/RESET
SCK
SI
14 Ld TSSOP
CS
1
14
SO
2
13
NC
3
12
NC
4 X5328/29 11
NC
5
10
WP
6
9
V_SS
7
8
V_CC
RESET/RESET
NC
NC
NC
SCK
SI
4
FN8132.1
October 17, 2005