X5328 Datasheet, PDF (14/21 Pages) Intersil Corporation – CPU Supervisor with 32Kbit SPI EEPROM

Serial Input Timing
CS
SCK
SI
t_LEAD
t_SU
t_H
MSB IN
X5328, X5329
t_RI
t_CS
t_LAG
t_FI
LSB IN
SO
High Impedance
Serial Output Timing
2.7-5.5V
Symbol
Parameter
Min.
Max.
Unit
f_SCK
Clock Frequency
0
2
MHz
t_DIS
Output Disable Time
250
ns
t_V
Output Valid from Clock Low
250
ns
t_HO
Output Hold Time
0
ns
t_RO(3)
Output Rise Time
100
ns
t_FO(3)
Output Fall Time
100
ns
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) t_WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Serial Output Timing
CS
SCK
t_CYC
t_WH
t_LAG
t_V
t_HO
t_WL
t_DIS
SO
MSB Out
MSB–1 Out
LSB Out
SI
ADDR
LSB IN
14
FN8132.1
October 17, 2005