ISL6726_14 Datasheet, PDF (4/20 Pages) Intersil Corporation – Active Clamp Forward PWM Controller

Internal Architecture
VREF
VDD
UVLOBIAS
GND
UVLO
INTERNAL
OT SHUTDOWN
130 - 150 C
VREF
5.00 V
1%
ON
DISABLE
1.00 V
+
INHIBIT
UV
-
EXT. SYNC
IRTC
RTC
OSCILLATOR
SYNC
SYNC
Bi-Directional
SYNC Circuit
SYNC OUT
Phase-Shifted
180 º
CLK
VREF
ICH
ON
CT
IDCH
DCLIM
ON
____
CLK
CT
CLK
+
-
ISET
CS
SLOPE
VERR
+
OC DETECT
-
VREF
SLOPE
VERROR
CS
OC
PWM
DUTY LIMIT
PWM OUT
SOFT-START
MODE
CLK
PWM
OUTPUT DELAY CONTROL
AND
STEERING LOGIC
OUT
DELAY
OUTCLAMP
VDD
OUTM
DELAY
OUTAC
CS
AVERAGE
CURRENT LIMIT
IOUT
IOUT
CURRENT
AMPLIFIER
-
FB
+ ISET
LEADING EDGE BLANKING
DISABLE
VREF
INHIBIT
UVLOBIAS
SOFT-START/
SOFT-STOP
ENABLE
SS
MODE