ISL6726_14 Datasheet, PDF (19/20 Pages) Intersil Corporation – Active Clamp Forward PWM Controller

ISL6726
Determine the downslope:
Downslope = 0.125V/1.6µs = 78mV/µs. Now determine the
amount of voltage that must be added to the current sense
signal by the end of the On time.
V_SLOPE
=
1_--
2
•
0.078
•
2.4
=
94 m V
(EQ. 14)
Therefore,
C_SLOPE(MIN)
=
18×10^–6 • ²----^.-⁴----^×----1---0---^–---⁶- ≈ 470pF
0.094
(EQ. 15)
An appropriate slope compensation capacitance for this example
would be 1/2 to 1/3 the calculated value, or between 150pF and
220pF.
Using MODE
The MODE pin configures the IC for standard or synchronous
rectification compatibility. If MODE is connected to VREF, standard
rectification compatibility is selected. Soft-stop and the minimum
duty cycle clamp are disabled. If MODE is connected to GND,
synchronous rectification compatibility is selected, and soft-stop
and the minimum duty cycle clamp are enabled.
Thermal Protection
An internal temperature sensor protects the device should the
junction temperature exceed +145°C. There is approximately
+15°C of hysteresis.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device.
A good ground plane must be employed. Use a ground layer if
possible. The power ground should be connected to the control
ground at one point. VDD should be bypassed directly to GND with
good high frequency capacitance, such as a ceramic capacitor. A
small ceramic capacitor is also recommended for DCLIM.
The OUTM, and OUTAC of ISL6726 are very fast signals, and
should have very short direct paths to the power MOSFETs in
order to minimize inductance in the PC board traces. The return
path should be as short as possible. The components at the Pins
of SS, DCLIM, UV, DELAY, CT, and RTC should be as physically
close as possible to the IC. Proximity to high di/dt loops and high
dv/dt nodes should be avoided.
The CS signal requires proper filtering and the PWB layout is
critical for normal operation of the current related functions. A
RC filter may be required. The time constant should be no greater
than 25ns to prevent incorrect average current information. If a
current sense transformer is used, both leads of the secondary
winding should be routed to the CS filter components and to the
IC pins. The transformer return should be connected via a
dedicated PC board trace to the GND pin rather than through the
ground plane.
If a current sense resistor in series with the switching FET source
is used, a low inductance resistor is recommended. The low level
signals must avoid the high current path.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
CHANGE
January 31, 2011 FN7654.0 Initial Release.
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19
FN7654.0
January 31, 2011