ISL6726_14 Datasheet, PDF (16/20 Pages) Intersil Corporation – Active Clamp Forward PWM Controller

ISL6726
The average current loop bandwidth is normally set much lower
than the switching frequency, typically less than 5kHz and
maybe as slow as a few hundred hertz, depending on the
application requirements. This is especially useful if the
application experiences large surges. The average current loop
can be set to the steady state overcurrent threshold and have a
time response that is longer than the required transient.
Under some conditions it will be necessary to clamp the FB pin
with a Schottky diode to signal ground. If the voltage loop causes
a fast decreasing transient on VERR, the feedback capacitor
between VERR and FB can cause a negative voltage on FB and
violate the absolute maximum rating.
Duty Cycle Clamp
MAXIMUM DUTY CYCLE CLAMP
DUTY CYCLE CLAMPED BY UV
1V 1.2V
UV = k*Vin
5V
FIGURE 14. DUTY CYCLE CLAMP
It is very important to control the maximum duty cycle of an
active clamp reset forward converter. The clamp capacitor and
drain-source voltage of the main switch is related to the duty
cycle D by Equation 7. If the duty cycle is not clamped, the FET
drain-source voltage can become quite high and overstress the
FET.
Vds = ₍---₁--^V---–-ⁱ--ⁿ-_D-----₎
(EQ. 7)
Without the input voltage dependent maximum duty cycle clamp
it is possible to have both high input voltage and high duty cycle
during input voltage or load transients. The duty cycle clamp
reduces the maximum duty cycle as the input voltage increases.
Whereas the maximum duty cycle at minimum input voltage is
large, it is not necessary, nor is it advantageous, to have the
same maximum duty cycle at maximum input voltage. The duty
cycle clamp allows the designer to provide a constant margin of
duty cycle headroom above the steady state operating point to
allow for adequate dynamic response without allowing so much
headroom that it can result in excessive voltage stress on the
FET.
During transients the situation is particularly bad, not only
because of the voltage stress on the power FETs, but also
because the clamp capacitor voltage is not at the steady state
voltage required to properly reset the transformer. The active
clamp forward topology is also know as the optimum reset
topology because the steady state clamp capacitor voltage is
exactly the value required to reset the core during the off time.
However, it can take many switching cycles before the clamp
capacitor voltage reaches a new steady state value after a
change in operating point. If the clamp capacitor voltage is lower
than required, the transformer core is not reset completely and
can lead to transformer saturation after a few switching cycles.
This condition occurs when the input voltage is rapidly
decreased, or when the output load is rapidly increased. Both of
these conditions result in a rapidly increasing duty cycle. If the
duty cycle can increase more quickly than the clamp capacitor
voltage can respond, the core will not be properly reset. One or
the other of these transients can be mitigated by the sizing of
the clamp capacitor value. Smaller values favor input voltage
transient behavior whereas larger values favor load transient
behavior. Most designs favor load transient behavior. In either
case, the maximum duty cycle clamp prevents large duty cycle
increases and limits transformer flux density and FET voltage
stress.
The main output PWM is controlled by the current and voltage
feedback signals. When the feedback loop demands maximum
duty cycle, the duty cycle is limited by the lesser of the input
voltage-dependent duty cycle limiter or the maximum duty cycle
limit of the controller, which is 80% by design.
The input voltage dependent duty cycle limit is inversely
proportional to the input voltage, as shown in Figure 15. The
voltage applied to UV determines the amplitude of the CT
sawtooth waveform, where CT_PEAK = 0.8 + 0.8 * UV. Since the
UV turn-on threshold is 1.00V, the minimum amplitude of CT is
1.60V. At UV = 4.00V, the amplitude of CT is 4.00V. The
maximum duty cycle clamp is determined by the voltage applied
to DCLIM and the amplitude of CT. If DCLIM is set to 1.60V or
greater, the maximum duty cycle is 80%. The maximum duty
cycle as a function of UV and DCLIM is:
D_MAX
=
=
0.8, DCLIM > 0.8 ⋅ UV + 0.8
D_-----C_----L_---I_--M_{-------–----}0_----._-8_{--, DCLIM ≤ 0.8 ⋅ UV + 0.8}
UV
(EQ. 8)
For most applications the maximum duty cycle will be set for the
minimum operating input voltage, and for which UV is set to
1.00V.
Consequently, the actual duty cycle of the main output, OUTM, is
the minimum of the current mode PWM comparator, the
maximum 80% duty cycle clamp of the controller, or the input
voltage dependent duty cycle clamp.
16
FN7654.0
January 31, 2011